A(0xE280, CPM1, TRICORE_FEATURE_13)
A(0xE300, CPM2, TRICORE_FEATURE_13)
A(0xE380, CPM3, TRICORE_FEATURE_13)
-/* memory Managment Registers */
+/* memory management registers */
A(0x8000, MMU_CON, TRICORE_FEATURE_13)
A(0x8004, MMU_ASI, TRICORE_FEATURE_13)
A(0x800C, MMU_TVA, TRICORE_FEATURE_13)
case OPCM_32_RR_LOGICAL_SHIFT:
decode_rr_logical_shift(env, ctx);
break;
- case OPCM_32_RR_ADRESS:
+ case OPCM_32_RR_ADDRESS:
decode_rr_address(env, ctx);
break;
case OPCM_32_RR_IDIRECT:
/* RR Format */
OPCM_32_RR_LOGICAL_SHIFT = 0x0f,
OPCM_32_RR_ACCUMULATOR = 0x0b,
- OPCM_32_RR_ADRESS = 0x01,
+ OPCM_32_RR_ADDRESS = 0x01,
OPCM_32_RR_DIVIDE = 0x4b,
OPCM_32_RR_IDIRECT = 0x2d,
/* RR1 Format */
OPC2_32_RR_XOR_LT_U = 0x32,
OPC2_32_RR_XOR_NE = 0x30,
};
-/* OPCM_32_RR_ADRESS */
+/* OPCM_32_RR_ADDRESS */
enum {
OPC2_32_RR_ADD_A = 0x01,
OPC2_32_RR_ADDSC_A = 0x60,