mmc: sdhci-pci-gli: A workaround to allow GL9755 to enter ASPM L1.2

When GL9755 enters ASPM L1 sub-states, it will stay at L1.1 and will not
enter L1.2. The workaround is to toggle PM state to allow GL9755 to enter
ASPM L1.2.

Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220414094945.457500-1-benchuanggli@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>

diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index d09728c..1499a64 100644 (file)
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -142,6 +142,9 @@
 #define PCI_GLI_9755_MISC          0x78
 #define   PCI_GLI_9755_MISC_SSC_OFF    BIT(26)
 
+#define PCI_GLI_9755_PM_CTRL     0xFC
+#define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
+
 #define GLI_MAX_TUNING_LOOP 40
 
 /* Genesys Logic chipset */
@@ -676,6 +679,13 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
                            GLI_9755_CFG2_L1DLY_VALUE);
        pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
 
+       /* toggle PM state to allow GL9755 to enter ASPM L1.2 */
+       pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
+       value |= PCI_GLI_9755_PM_STATE;
+       pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
+       value &= ~PCI_GLI_9755_PM_STATE;
+       pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
+
        gl9755_wt_off(pdev);
 }