hdmitx: add prbs debug function
authorYi Zhou <yi.zhou@amlogic.com>
Mon, 26 Mar 2018 07:53:21 +0000 (15:53 +0800)
committerYixun Lan <yixun.lan@amlogic.com>
Fri, 30 Mar 2018 07:49:34 +0000 (23:49 -0800)
PD#163020: hdmitx: add prbs debug function

method(in kernel):
echo 444,8bit > /sys/class/amhdmitx/amhdmitx0/attr
echo 1080p60hz > /sys/class/display/mode
echo prbs > /sys/class/amhdmitx/amhdmitx0/debug

Change-Id: I07fe69166383105ec3df74fc7df24b95b1a3ab84
Signed-off-by: Yi Zhou <yi.zhou@amlogic.com>
drivers/amlogic/media/vout/hdmitx/hdmi_tx_20/hw/hdmi_tx_hw.c

index 7c381d8..d24a9f5 100644 (file)
@@ -2944,6 +2944,29 @@ static void hdmitx_debug(struct hdmitx_dev *hdev, const char *buf)
                if (buf[1] == 'h')
                        value = hdmitx_rd_reg(adr);
                pr_info(HW "%s reg[%lx]=%lx\n", "HDMI", adr, value);
+       } else if (strncmp(tmpbuf, "prbs", 4) == 0) {
+               switch (hdev->chip_type) {
+               case MESON_CPU_ID_G12A:
+                       for (i = 0; i < 4; i++) {
+                               hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000f);
+                               hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000e);
+                               hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x03904002);
+                               hd_write_reg(P_HHI_HDMI_PHY_CNTL4, 0x0001efff
+                                       | (i << 20));
+                               hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0xef904002);
+                               mdelay(10);
+                               if (i > 0)
+                                       pr_info("prbs D[%d]:%x\n", i - 1,
+                                               hd_read_reg
+                                               (P_HHI_HDMI_PHY_STATUS));
+                               else
+                                       pr_info("prbs clk :%x\n", hd_read_reg
+                                               (P_HHI_HDMI_PHY_STATUS));
+                       }
+                       break;
+               default:
+                       break;
+               }
        }
 }