;; This shadows the processor_type enumeration, so changes must be made
;; to i386.h at the same time.
-(define_attr "type" "integer,fld,fpop,fpdiv"
+(define_attr "type" "integer,idiv,imul,fld,fpop,fpdiv,fpmul"
(const_string "integer"))
;; Functional units
+; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
+; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
+
+; pentiumpro has a reservation station with 5 ports
+; port 0 has integer, float add, integer divide, float divide, float
+; multiply, and shifter units.
+; port 1 has integer, and jump units.
+; port 2 has the load address generation unit
+; ports 3 and 4 have the store address generation units
+
+; pentium has two integer pipelines, the main u pipe and the secondary v pipe.
+; and a float pipeline
+
;; Floating point
(define_function_unit "fp" 1 0
- (and (eq_attr "type" "fpop") (eq_attr "cpu" "!pentium"))
+ (and (eq_attr "type" "fpop") (eq_attr "cpu" "i386,i486"))
5 5)
(define_function_unit "fp" 1 0
- (and (eq_attr "type" "fpop") (eq_attr "cpu" "pentium"))
+ (and (eq_attr "type" "fpop") (eq_attr "cpu" "pentium,pentiumpro"))
3 0)
(define_function_unit "fp" 1 0
+ (and (eq_attr "type" "fpmul") (eq_attr "cpu" "pentium"))
+ 7 0)
+
+(define_function_unit "fp" 1 0
+ (and (eq_attr "type" "fpmul") (eq_attr "cpu" "pentiumpro"))
+ 5 0)
+
+(define_function_unit "fp" 1 0
+ (and (eq_attr "type" "idiv") (eq_attr "cpu" "pentiumpro"))
+ 10 10)
+
+(define_function_unit "fp" 1 0
+ (and (eq_attr "type" "imul") (eq_attr "cpu" "pentiumpro"))
+ 6 0)
+
+(define_function_unit "fp" 1 0
(eq_attr "type" "fpdiv")
10 10)
return output_move_double (operands);
}"
-[(set_attr "type" "fld")])
+ [(set_attr "type" "fld")])
/* Assembler has weird restrictions. */
return AS2 (imul%W0,%2,%0);
return AS3 (imul%W0,%2,%1,%0);
-}")
+}"
+ [(set_attr "type" "imul")])
(define_insn "mulsi3"
[(set (match_operand:SI 0 "register_operand" "=r,r")
/* Assembler has weird restrictions. */
return AS2 (imul%L0,%2,%0);
return AS3 (imul%L0,%2,%1,%0);
-}")
+}"
+ [(set_attr "type" "imul")])
(define_insn "umulqihi3"
[(set (match_operand:HI 0 "register_operand" "=a")
(mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "%0"))
(zero_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))]
""
- "mul%B0 %2")
+ "mul%B0 %2"
+ [(set_attr "type" "imul")])
(define_insn "mulqihi3"
[(set (match_operand:HI 0 "register_operand" "=a")
(mult:HI (sign_extend:HI (match_operand:QI 1 "register_operand" "%0"))
(sign_extend:HI (match_operand:QI 2 "nonimmediate_operand" "qm"))))]
""
- "imul%B0 %2")
+ "imul%B0 %2"
+ [(set_attr "type" "imul")])
(define_insn "umulsidi3"
[(set (match_operand:DI 0 "register_operand" "=A")
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0"))
(zero_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))]
"TARGET_WIDE_MULTIPLY"
- "mul%L0 %2")
+ "mul%L0 %2"
+ [(set_attr "type" "imul")])
(define_insn "mulsidi3"
[(set (match_operand:DI 0 "register_operand" "=A")
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0"))
(sign_extend:DI (match_operand:SI 2 "nonimmediate_operand" "rm"))))]
"TARGET_WIDE_MULTIPLY"
- "imul%L0 %2")
+ "imul%L0 %2"
+ [(set_attr "type" "imul")])
(define_insn "umulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "=d")
(const_int 32))))
(clobber (match_scratch:SI 3 "=a"))]
"TARGET_WIDE_MULTIPLY"
- "mul%L0 %2")
+ "mul%L0 %2"
+ [(set_attr "type" "imul")])
(define_insn "smulsi3_highpart"
[(set (match_operand:SI 0 "register_operand" "=d")
(const_int 32))))
(clobber (match_scratch:SI 3 "=a"))]
"TARGET_WIDE_MULTIPLY"
- "imul%L0 %2")
+ "imul%L0 %2"
+ [(set_attr "type" "imul")])
;; The patterns that match these are at the end of this file.
(udiv:QI (match_operand:HI 1 "register_operand" "0")
(match_operand:QI 2 "nonimmediate_operand" "qm")))]
""
- "div%B0 %2")
+ "div%B0 %2"
+ [(set_attr "type" "idiv")])
;; The patterns that match these are at the end of this file.
output_asm_insn (\"cltd\", operands);
#endif
return AS1 (idiv%L0,%2);
-}")
+}"
+ [(set_attr "type" "idiv")])
(define_insn "divmodhi4"
[(set (match_operand:HI 0 "register_operand" "=a")
(set (match_operand:HI 3 "register_operand" "=&d")
(mod:HI (match_dup 1) (match_dup 2)))]
""
- "cwtd\;idiv%W0 %2")
+ "cwtd\;idiv%W0 %2"
+ [(set_attr "type" "idiv")])
;; ??? Can we make gcc zero extend operand[0]?
(define_insn "udivmodsi4"
{
output_asm_insn (AS2 (xor%L3,%3,%3), operands);
return AS1 (div%L0,%2);
-}")
+}"
+ [(set_attr "type" "idiv")])
;; ??? Can we make gcc zero extend operand[0]?
(define_insn "udivmodhi4"
{
output_asm_insn (AS2 (xor%W0,%3,%3), operands);
return AS1 (div%W0,%2);
-}")
+}"
+ [(set_attr "type" "idiv")])
/*
;;this should be a valid double division which we may want to add
(set (match_operand:SI 3 "register_operand" "=d")
(umod:SI (match_dup 1) (match_dup 2)))]
""
- "div%L0 %2,%0")
+ "div%L0 %2,%0"
+ [(set_attr "type" "idiv")])
*/
\f
;;- and instructions
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]
"* return output_387_binary_op (insn, operands);"
[(set (attr "type")
(cond [(match_operand:DF 3 "is_mul" "")
- (const_string "fpop")
+ (const_string "fpmul")
(match_operand:DF 3 "is_div" "")
(const_string "fpdiv")
]