Otherwise the EOP interrupt on non-AID0 cannot route to IH0.
Signed-off-by: Le Ma <le.ma@amd.com>
Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
static void gfx_v9_4_3_init_golden_registers(struct amdgpu_device *adev)
{
+ int i;
+ for (i = 2; i < adev->gfx.num_xcd; i++)
+ WREG32_SOC15(GC, i, regGRBM_MCM_ADDR, 0x4);
}
static void gfx_v9_4_3_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,