ddr: marvell: a38x: allow board specific ODT configuration

commit 2d3b9437cf38c06c4330e0de07f29476197f5e04 upstream.

The ODT enable heuristic based on active chip-selects is not always
correct. Some board might use two chip-selects, but have only one ODT
line connected. Allow board specific mv_ddr_topology_map to directly set
the ODT configuration register value.

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Moti Buskila <motib@marvell.com>
Reviewed-by: Nadav Haklai <Nadav.Haklai@cavium.com>
Reviewed-by: Kostya Porotchkin <Kostya.Porotchkin@cavium.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Tested-by: Chris Packham <chris.packham@alliedtelesis.co.nz>

diff --git a/drivers/ddr/marvell/a38x/ddr3_init.c b/drivers/ddr/marvell/a38x/ddr3_init.c
index a971cc1..7488770 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr3_init.c
+++ b/drivers/ddr/marvell/a38x/ddr3_init.c
@@ -104,6 +104,7 @@ int ddr3_init(void)
 static int mv_ddr_training_params_set(u8 dev_num)
 {
        struct tune_train_params params;
+       struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
        int status;
        u32 cs_num;
        int ck_delay;
@@ -136,6 +137,10 @@ static int mv_ddr_training_params_set(u8 dev_num)
        if (ck_delay > 0)
                params.ck_delay = ck_delay;
 
+       /* Use platform specific override ODT value */
+       if (tm->odt_config)
+               params.g_odt_config = tm->odt_config;
+
        status = ddr3_tip_tune_training_params(dev_num, &params);
        if (MV_OK != status) {
                printf("%s Training Sequence - FAILED\n", ddr_type);

diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h
index 342c2cf..3991fec 100644 (file)
--- a/drivers/ddr/marvell/a38x/ddr_topology_def.h
+++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h
@@ -125,6 +125,9 @@ struct mv_ddr_topology_map {
        /* electrical parameters */
        unsigned int electrical_data[MV_DDR_EDATA_LAST];
 
+       /* ODT configuration */
+       u32 odt_config;
+
        /* Clock enable mask */
        u32 clk_enable;