[AMDGPU] Regenerate shared-op-cycle.ll test

diff --git a/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll b/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll
index f9a72b4..d04b82a 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll
+++ b/llvm/test/CodeGen/AMDGPU/shared-op-cycle.ll
@@ -1,10 +1,22 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-; CHECK: {{^}}main:
-; CHECK: MULADD_IEEE *
-; CHECK-NOT: MULADD_IEEE *
-
 define amdgpu_vs void @main(<4 x float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2) {
+; CHECK-LABEL: main:
+; CHECK:       ; %bb.0:
+; CHECK-NEXT:    CALL_FS
+; CHECK-NEXT:    ALU 7, @4, KC0[], KC1[]
+; CHECK-NEXT:    EXPORT T0.X___
+; CHECK-NEXT:    CF_END
+; CHECK-NEXT:    ALU clause starting at 4:
+; CHECK-NEXT:     MULADD_IEEE T0.X, T0.W, T0.W, literal.x,
+; CHECK-NEXT:     MULADD_IEEE T0.Y, T1.W, T1.W, literal.x, BS:VEC_120/SCL_212
+; CHECK-NEXT:     MULADD_IEEE * T0.Z, T2.W, T2.W, literal.x, BS:VEC_201
+; CHECK-NEXT:    1073741824(2.000000e+00), 0(0.000000e+00)
+; CHECK-NEXT:     DOT4 T0.X, T0.X, T0.X,
+; CHECK-NEXT:     DOT4 T0.Y (MASKED), T0.Y, T0.Y,
+; CHECK-NEXT:     DOT4 T0.Z (MASKED), T0.Z, T0.Z,
+; CHECK-NEXT:     DOT4 * T0.W (MASKED), T0.W, T0.W,
    %w0 = extractelement <4 x float> %reg0, i32 3
    %w1 = extractelement <4 x float> %reg1, i32 3
    %w2 = extractelement <4 x float> %reg2, i32 3