drm/amdgpu/athub2: enable athub2 clock gating

Enable athub2 clock gating and light sleep

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index e3fde4a..0238998 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -135,6 +135,10 @@ amdgpu-y += \
        amdgpu_vcn.o \
        vcn_v1_0.o
 
+# add ATHUB block
+amdgpu-y += \
+       athub_v2_0.o
+
 # add amdkfd interfaces
 amdgpu-y += amdgpu_amdkfd.o
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index e0df2bc..9f4ed75 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -64,6 +64,9 @@ static const struct cg_flag_name clocks[] = {
        {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
        {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
        {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
+
+       {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
+       {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
        {0, NULL},
 };
 

diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
new file mode 100644 (file)
index 0000000..89b32b6
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "amdgpu.h"
+#include "athub_v2_0.h"
+
+#include "athub/athub_2_0_0_offset.h"
+#include "athub/athub_2_0_0_sh_mask.h"
+#include "athub/athub_2_0_0_default.h"
+#include "navi10_enum.h"
+
+#include "soc15_common.h"
+
+static void
+athub_v2_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
+                                           bool enable)
+{
+       uint32_t def, data;
+
+       def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+
+       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+               data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
+       else
+               data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
+
+       if (def != data)
+               WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
+}
+
+static void
+athub_v2_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
+                                          bool enable)
+{
+       uint32_t def, data;
+
+       def = data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+
+       if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
+           (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
+               data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
+       else
+               data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
+
+       if (def != data)
+               WREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL, data);
+}
+
+int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
+                              enum amd_clockgating_state state)
+{
+       if (amdgpu_sriov_vf(adev))
+               return 0;
+
+       switch (adev->asic_type) {
+       case CHIP_NAVI10:
+               athub_v2_0_update_medium_grain_clock_gating(adev,
+                               state == AMD_CG_STATE_GATE ? true : false);
+               athub_v2_0_update_medium_grain_light_sleep(adev,
+                               state == AMD_CG_STATE_GATE ? true : false);
+               break;
+       default:
+               break;
+       }
+
+       return 0;
+}
+
+void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags)
+{
+       int data;
+
+       /* AMD_CG_SUPPORT_ATHUB_MGCG */
+       data = RREG32_SOC15(ATHUB, 0, mmATHUB_MISC_CNTL);
+       if (data & ATHUB_MISC_CNTL__CG_ENABLE_MASK)
+               *flags |= AMD_CG_SUPPORT_ATHUB_MGCG;
+
+       /* AMD_CG_SUPPORT_ATHUB_LS */
+       if (data & ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK)
+               *flags |= AMD_CG_SUPPORT_ATHUB_LS;
+}

diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v2_0.h b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.h
new file mode 100644 (file)
index 0000000..02932c1
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v2_0.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright 2019 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef __ATHUB_V2_0_H__
+#define __ATHUB_V2_0_H__
+
+int athub_v2_0_set_clockgating(struct amdgpu_device *adev,
+                              enum amd_clockgating_state state);
+void athub_v2_0_get_clockgating(struct amdgpu_device *adev, u32 *flags);
+
+#endif

diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 15fbb2d..1e63835 100644 (file)
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -96,6 +96,8 @@ enum amd_powergating_state {
 #define AMD_CG_SUPPORT_HDP_DS                  (1 << 25)
 #define AMD_CG_SUPPORT_HDP_SD                  (1 << 26)
 #define AMD_CG_SUPPORT_IH_CG                   (1 << 27)
+#define AMD_CG_SUPPORT_ATHUB_LS                        (1 << 28)
+#define AMD_CG_SUPPORT_ATHUB_MGCG              (1 << 29)
 /* PG flags */
 #define AMD_PG_SUPPORT_GFX_PG                  (1 << 0)
 #define AMD_PG_SUPPORT_GFX_SMG                 (1 << 1)