[CLKID_HCODEC_MUX - CLKID_HCODEC_P0_MUX] = &hcodec_mux.hw,
};
-/* cts_hevc_clk */
+/* cts_hevcb_clk */
static struct clk_mux hevc_p0_mux = {
.reg = (void *)HHI_VDEC2_CLK_CNTL,
.mask = 0x7,
[CLKID_HEVC_MUX - CLKID_HEVC_P0_MUX] = &hevc_mux.hw,
};
+/* cts_hevcf_clk */
+static struct clk_mux hevcf_p0_mux = {
+ .reg = (void *)HHI_VDEC2_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "hevcf_p0_mux",
+ .ops = &clk_mux_ops,
+ .parent_names = g12a_dec_parent_names,
+ .num_parents = 8,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_divider hevcf_p0_div = {
+ .reg = (void *)HHI_VDEC2_CLK_CNTL,
+ .shift = 0,
+ .width = 7,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "hevcf_p0_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "hevcf_p0_mux" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_gate hevcf_p0_gate = {
+ .reg = (void *)HHI_VDEC2_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data) {
+ .name = "hevcf_p0_gate",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "hevcf_p0_div" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_mux hevcf_p1_mux = {
+ .reg = (void *)HHI_VDEC4_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 9,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "hevcf_p1_mux",
+ .ops = &clk_mux_ops,
+ .parent_names = g12a_dec_parent_names,
+ .num_parents = 8,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_divider hevcf_p1_div = {
+ .reg = (void *)HHI_VDEC4_CLK_CNTL,
+ .shift = 0,
+ .width = 7,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "hevcf_p1_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "hevcf_p1_mux" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_gate hevcf_p1_gate = {
+ .reg = (void *)HHI_VDEC4_CLK_CNTL,
+ .bit_idx = 8,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data) {
+ .name = "hevcf_p1_gate",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "hevcf_p1_div" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_mux hevcf_mux = {
+ .reg = (void *)HHI_VDEC4_CLK_CNTL,
+ .mask = 0x1,
+ .shift = 15,
+ .lock = &clk_lock,
+ .flags = CLK_PARENT_ALTERNATE,
+ .hw.init = &(struct clk_init_data){
+ .name = "hevcf_mux",
+ .ops = &meson_clk_mux_ops,
+ .parent_names = (const char *[]){ "hevcf_p0_composite",
+ "hevcf_p1_composite"},
+ .num_parents = 2,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_hw *hevcf_clk_hws[] = {
+ [CLKID_HEVCF_P0_MUX - CLKID_HEVCF_P0_MUX] = &hevcf_p0_mux.hw,
+ [CLKID_HEVCF_P0_DIV - CLKID_HEVCF_P0_MUX] = &hevcf_p0_div.hw,
+ [CLKID_HEVCF_P0_GATE - CLKID_HEVCF_P0_MUX] = &hevcf_p0_gate.hw,
+ [CLKID_HEVCF_P1_MUX - CLKID_HEVCF_P0_MUX] = &hevcf_p1_mux.hw,
+ [CLKID_HEVCF_P1_DIV - CLKID_HEVCF_P0_MUX] = &hevcf_p1_div.hw,
+ [CLKID_HEVCF_P1_GATE - CLKID_HEVCF_P0_MUX] = &hevcf_p1_gate.hw,
+ [CLKID_HEVCF_MUX - CLKID_HEVCF_P0_MUX] = &hevcf_mux.hw,
+};
+
static const char * const vpu_parent_names[] = { "fclk_div3",
"fclk_div4", "fclk_div5", "fclk_div7", "null", "null",
"null", "null"};
hevc_p1_gate.reg = clk_base + (u64)(hevc_p1_gate.reg);
hevc_mux.reg = clk_base + (u64)(hevc_mux.reg);
+ /* cts_hevcf_clk */
+ hevcf_p0_mux.reg = clk_base + (u64)(hevcf_p0_mux.reg);
+ hevcf_p0_div.reg = clk_base + (u64)(hevcf_p0_div.reg);
+ hevcf_p0_gate.reg = clk_base + (u64)(hevcf_p0_gate.reg);
+ hevcf_p1_mux.reg = clk_base + (u64)(hevcf_p1_mux.reg);
+ hevcf_p1_div.reg = clk_base + (u64)(hevcf_p1_div.reg);
+ hevcf_p1_gate.reg = clk_base + (u64)(hevcf_p1_gate.reg);
+ hevcf_mux.reg = clk_base + (u64)(hevcf_mux.reg);
+
/* cts_vpu_clk */
vpu_p0_mux.reg = clk_base + (u64)(vpu_p0_mux.reg);
vpu_p0_div.reg = clk_base + (u64)(vpu_p0_div.reg);
panic("%s: %d clk_register hevc_mux error\n",
__func__, __LINE__);
+ /* cts_hevcf_clk */
+ clks[CLKID_HEVCF_P0_COMP] = clk_register_composite(NULL,
+ "hevcf_p0_composite",
+ g12a_dec_parent_names, 8,
+ hevcf_clk_hws[CLKID_HEVCF_P0_MUX - CLKID_HEVCF_P0_MUX],
+ &clk_mux_ops,
+ hevcf_clk_hws[CLKID_HEVCF_P0_DIV - CLKID_HEVCF_P0_MUX],
+ &clk_divider_ops,
+ hevcf_clk_hws[CLKID_HEVCF_P0_GATE - CLKID_HEVCF_P0_MUX],
+ &clk_gate_ops, 0);
+ if (IS_ERR(clks[CLKID_HEVCF_P0_COMP]))
+ panic("%s: %d clk_register_composite hevcf_p0_composite error\n",
+ __func__, __LINE__);
+
+ clks[CLKID_HEVCF_P1_COMP] = clk_register_composite(NULL,
+ "hevcf_p1_composite",
+ g12a_dec_parent_names, 8,
+ hevcf_clk_hws[CLKID_HEVCF_P1_MUX - CLKID_HEVCF_P0_MUX],
+ &clk_mux_ops,
+ hevcf_clk_hws[CLKID_HEVCF_P1_DIV - CLKID_HEVCF_P0_MUX],
+ &clk_divider_ops,
+ hevcf_clk_hws[CLKID_HEVCF_P1_GATE - CLKID_HEVCF_P0_MUX],
+ &clk_gate_ops, 0);
+ if (IS_ERR(clks[CLKID_HEVCF_P1_COMP]))
+ panic("%s: %d clk_register_composite hevcf_p1_composite error\n",
+ __func__, __LINE__);
+
+ clks[CLKID_HEVCF_MUX] = clk_register(NULL,
+ hevcf_clk_hws[CLKID_HEVCF_MUX - CLKID_HEVCF_P0_MUX]);
+ if (IS_ERR(clks[CLKID_HEVCF_MUX]))
+ panic("%s: %d clk_register hevcf_mux error\n",
+ __func__, __LINE__);
+
/* cts_vpu_clk */
clks[CLKID_VPU_P0_COMP] = clk_register_composite(NULL,
"vpu_p0_composite",
},
};
+static const char * const spicc_parent_names[] = { "xtal",
+ "clk81", "fclk_div4", "fclk_div3", "fclk_div2", "fclk_div5",
+ "fclk_div7", "gp0"};
+
+/* spicc clk */
+static struct clk_mux g12a_spicc0_mux = {
+ .reg = (void *)HHI_SPICC_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 7,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "spicc0_mux",
+ .ops = &clk_mux_ops,
+ .parent_names = spicc_parent_names,
+ .num_parents = 8,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_divider g12a_spicc0_div = {
+ .reg = (void *)HHI_SPICC_CLK_CNTL,
+ .shift = 0,
+ .width = 6,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "spicc0_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "spicc0_mux" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_gate g12a_spicc0_gate = {
+ .reg = (void *)HHI_SPICC_CLK_CNTL,
+ .bit_idx = 6,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data) {
+ .name = "spicc0_gate",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "spicc0_div" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_mux g12a_spicc1_mux = {
+ .reg = (void *)HHI_SPICC_CLK_CNTL,
+ .mask = 0x7,
+ .shift = 23,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "spicc1_mux",
+ .ops = &clk_mux_ops,
+ .parent_names = spicc_parent_names,
+ .num_parents = 8,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_divider g12a_spicc1_div = {
+ .reg = (void *)HHI_SPICC_CLK_CNTL,
+ .shift = 16,
+ .width = 6,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data){
+ .name = "spicc_p1_div",
+ .ops = &clk_divider_ops,
+ .parent_names = (const char *[]){ "spicc_p1_mux" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+static struct clk_gate g12a_spicc1_gate = {
+ .reg = (void *)HHI_SPICC_CLK_CNTL,
+ .bit_idx = 22,
+ .lock = &clk_lock,
+ .hw.init = &(struct clk_init_data) {
+ .name = "spicc_p1_gate",
+ .ops = &clk_gate_ops,
+ .parent_names = (const char *[]){ "spicc_p1_div" },
+ .num_parents = 1,
+ .flags = CLK_GET_RATE_NOCACHE,
+ },
+};
+
+
void meson_g12a_misc_init(void)
{
/* Populate base address for reg */
g12a_ts_clk_div.reg = clk_base + (u64)(g12a_ts_clk_div.reg);
g12a_ts_clk_gate.reg = clk_base + (u64)(g12a_ts_clk_gate.reg);
+ g12a_spicc0_mux.reg = clk_base + (u64)(g12a_spicc0_mux.reg);
+ g12a_spicc0_div.reg = clk_base + (u64)(g12a_spicc0_div.reg);
+ g12a_spicc0_gate.reg = clk_base + (u64)(g12a_spicc0_gate.reg);
+ g12a_spicc1_mux.reg = clk_base + (u64)(g12a_spicc1_mux.reg);
+ g12a_spicc1_div.reg = clk_base + (u64)(g12a_spicc1_div.reg);
+ g12a_spicc1_gate.reg = clk_base + (u64)(g12a_spicc1_gate.reg);
+
clks[CLKID_TS_COMP] = clk_register_composite(NULL,
"ts_comp",
ts_parent_names, 1,
panic("%s: %d clk_register_composite ts_comp error\n",
__func__, __LINE__);
+ clks[CLKID_SPICC0_COMP] = clk_register_composite(NULL,
+ "spicc0_comp",
+ spicc_parent_names, 8,
+ &g12a_spicc0_mux.hw,
+ &clk_mux_ops,
+ &g12a_spicc0_div.hw,
+ &clk_divider_ops,
+ &g12a_spicc0_gate.hw,
+ &clk_gate_ops, 0);
+ if (IS_ERR(clks[CLKID_SPICC0_COMP]))
+ panic("%s: %d clk_register_composite spicc0_comp error\n",
+ __func__, __LINE__);
+
+ clks[CLKID_SPICC1_COMP] = clk_register_composite(NULL,
+ "spicc1_comp",
+ spicc_parent_names, 8,
+ &g12a_spicc1_mux.hw,
+ &clk_mux_ops,
+ &g12a_spicc1_div.hw,
+ &clk_divider_ops,
+ &g12a_spicc1_gate.hw,
+ &clk_gate_ops, 0);
+ if (IS_ERR(clks[CLKID_SPICC1_COMP]))
+ panic("%s: %d clk_register_composite spicc1_comp error\n",
+ __func__, __LINE__);
+
pr_info("%s: done.\n", __func__);
}
#define CLKID_HCODEC_P1_GATE (CLKID_MEDIA_BASE + 40)
#define CLKID_HCODEC_P1_COMP (CLKID_MEDIA_BASE + 41)
#define CLKID_HCODEC_MUX (CLKID_MEDIA_BASE + 42)
+/*HEVCB_CLK*/
#define CLKID_HEVC_P0_MUX (CLKID_MEDIA_BASE + 43)
#define CLKID_HEVC_P0_DIV (CLKID_MEDIA_BASE + 44)
#define CLKID_HEVC_P0_GATE (CLKID_MEDIA_BASE + 45)
#define CLKID_HEVC_P1_GATE (CLKID_MEDIA_BASE + 49)
#define CLKID_HEVC_P1_COMP (CLKID_MEDIA_BASE + 50)
#define CLKID_HEVC_MUX (CLKID_MEDIA_BASE + 51)
+/*HEVCF_CLK*/
+#define CLKID_HEVCF_P0_MUX (CLKID_MEDIA_BASE + 52)
+#define CLKID_HEVCF_P0_DIV (CLKID_MEDIA_BASE + 53)
+#define CLKID_HEVCF_P0_GATE (CLKID_MEDIA_BASE + 54)
+#define CLKID_HEVCF_P0_COMP (CLKID_MEDIA_BASE + 55)
+#define CLKID_HEVCF_P1_MUX (CLKID_MEDIA_BASE + 56)
+#define CLKID_HEVCF_P1_DIV (CLKID_MEDIA_BASE + 57)
+#define CLKID_HEVCF_P1_GATE (CLKID_MEDIA_BASE + 58)
+#define CLKID_HEVCF_P1_COMP (CLKID_MEDIA_BASE + 59)
+#define CLKID_HEVCF_MUX (CLKID_MEDIA_BASE + 60)
-#define CLKID_MISC_BASE (CLKID_MEDIA_BASE + 52)
-#define CLKID_SPICC_MUX (CLKID_MISC_BASE + 0)
-#define CLKID_SPICC_DIV (CLKID_MISC_BASE + 1)
-#define CLKID_SPICC_GATE (CLKID_MISC_BASE + 2)
-#define CLKID_SPICC_COMP (CLKID_MISC_BASE + 3)
-#define CLKID_TS_COMP (CLKID_MISC_BASE + 4)
+#define CLKID_MISC_BASE (CLKID_MEDIA_BASE + 61)
+#define CLKID_SPICC0_MUX (CLKID_MISC_BASE + 0)
+#define CLKID_SPICC0_DIV (CLKID_MISC_BASE + 1)
+#define CLKID_SPICC0_GATE (CLKID_MISC_BASE + 2)
+#define CLKID_SPICC0_COMP (CLKID_MISC_BASE + 3)
+#define CLKID_SPICC1_MUX (CLKID_MISC_BASE + 4)
+#define CLKID_SPICC1_DIV (CLKID_MISC_BASE + 5)
+#define CLKID_SPICC1_GATE (CLKID_MISC_BASE + 6)
+#define CLKID_SPICC1_COMP (CLKID_MISC_BASE + 7)
+#define CLKID_TS_COMP (CLKID_MISC_BASE + 8)
-#define CLKID_AO_BASE (CLKID_MISC_BASE + 5)
+#define CLKID_AO_BASE (CLKID_MISC_BASE + 9)
#define CLKID_AO_CLK81 (CLKID_AO_BASE + 0)
#define CLKID_SARADC_MUX (CLKID_AO_BASE + 1)
#define CLKID_SARADC_DIV (CLKID_AO_BASE + 2)