Summary: AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model. This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000.
Reviewers: t.p.northover, peter.smith, rovka
Subscribers: salim.nasser, aemerson, llvm-commits, rengolin
Differential Revision: https://reviews.llvm.org/D24702
llvm-svn: 282661
++MCNumFixups;
+ // Set the shift bit of the add instruction for relocation types
+ // R_AARCH64_TLSLE_ADD_TPREL_HI12 and R_AARCH64_TLSLD_ADD_DTPREL_HI12.
+ if (const AArch64MCExpr *A64E = dyn_cast<AArch64MCExpr>(Expr)) {
+ AArch64MCExpr::VariantKind RefKind = A64E->getKind();
+ if (RefKind == AArch64MCExpr::VK_TPREL_HI12 ||
+ RefKind == AArch64MCExpr::VK_DTPREL_HI12)
+ ShiftVal = 12;
+ }
return ShiftVal == 0 ? 0 : (1 << ShiftVal);
}
--- /dev/null
+// RUN: llvm-mc -triple=aarch64-none-linux-gnu -filetype=obj < %s -o - | \
+// RUN: llvm-objdump -r -d - | FileCheck %s
+
+ // TLS add TPREL
+ add x2, x1, #:tprel_hi12:var
+// CHECK: add x2, x1, #0, lsl #12
+// CHECK-NEXT: R_AARCH64_TLSLE_ADD_TPREL_HI12 var
+
+ // TLS add DTPREL
+ add x4, x3, #:dtprel_hi12:var
+// CHECK: add x4, x3, #0, lsl #12
+// CHECK-NEXT: R_AARCH64_TLSLD_ADD_DTPREL_HI12 var