drm/exynos: Properly report supported formats for each device

Exynos DRM reported that all planes for all supported sub-devices supports
only three pixel formats: XRGB24, ARGB24 and NV12. This patch lets each
Exynos DRM sub-drivers to provide the list of supported pixel formats
and registers this list to DRM core.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
[jy0922.shim: backported from original mainline commit]
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Change-Id: I7f486b9f2d776a8fdd8cb0c758100eba8de31ef6

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 77c8d576be03f742f33d45e457cd5fbfe5691452..82e722697212af5d0a4f1d93ed4f188d3fba57b2 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -39,6 +39,13 @@ static const char * const decon_clks_name[] = {
        "sclk_decon_eclk",
 };
 
+static const uint32_t decon_formats[] = {
+       DRM_FORMAT_XRGB1555,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_ARGB8888,
+};
+
 struct exynos5433_decon_driver_data {
        enum exynos_drm_output_type type;
        enum exynos_drm_trigger_type trg_type;
@@ -691,7 +698,8 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
                type = (zpos == drv_data->first_win) ? DRM_PLANE_TYPE_PRIMARY :
                        DRM_PLANE_TYPE_OVERLAY;
                ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
-                                       1 << ctx->pipe, type, zpos);
+                               1 << ctx->pipe, type, decon_formats,
+                               ARRAY_SIZE(decon_formats), zpos);
                if (ret)
                        return ret;
        }

diff --git a/drivers/gpu/drm/exynos/exynos7_drm_decon.c b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
index 599c1cd171dffa5eaa1a0bbf650090b0c1d32712..e278ef9f8d0a9a7d4826542156df03bd0b160443 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos7_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos7_drm_decon.c
@@ -96,6 +96,18 @@ static const struct of_device_id decon_driver_dt_match[] = {
 };
 MODULE_DEVICE_TABLE(of, decon_driver_dt_match);
 
+static const uint32_t decon_formats[] = {
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_XBGR8888,
+       DRM_FORMAT_RGBX8888,
+       DRM_FORMAT_BGRX8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_ABGR8888,
+       DRM_FORMAT_RGBA8888,
+       DRM_FORMAT_BGRA8888,
+};
+
 static inline struct decon_driver_data *drm_decon_get_driver_data(
        struct platform_device *pdev)
 {
@@ -940,7 +952,8 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
                type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
                                                DRM_PLANE_TYPE_OVERLAY;
                ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
-                                       1 << ctx->pipe, type, zpos);
+                                       1 << ctx->pipe, type, decon_formats,
+                                       ARRAY_SIZE(decon_formats), zpos);
                if (ret)
                        return ret;
        }

diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 0d0efcdc5d79cb029272b9429b1c9b919773f7f9..c22e70f0928a16a93ef22fecd7a86f6b39635526 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -187,6 +187,14 @@ static const struct of_device_id fimd_driver_dt_match[] = {
 };
 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 
+static const uint32_t fimd_formats[] = {
+       DRM_FORMAT_C8,
+       DRM_FORMAT_XRGB1555,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_ARGB8888,
+};
+
 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
        struct platform_device *pdev)
 {
@@ -1038,7 +1046,8 @@ static int fimd_bind(struct device *dev, struct device *master, void *data)
                type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
                                                DRM_PLANE_TYPE_OVERLAY;
                ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
-                                       1 << ctx->pipe, type, zpos);
+                                       1 << ctx->pipe, type, fimd_formats,
+                                       ARRAY_SIZE(fimd_formats), zpos);
                if (ret)
                        return ret;
        }

diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.c b/drivers/gpu/drm/exynos/exynos_drm_plane.c
index b1180fbe754690f700c124bdd50f72adb28d2295..7672f3aa2c4859756d5cae7f6e94fb579a27cf3f 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.c
@@ -19,12 +19,6 @@
 #include "exynos_drm_gem.h"
 #include "exynos_drm_plane.h"
 
-static const uint32_t formats[] = {
-       DRM_FORMAT_XRGB8888,
-       DRM_FORMAT_ARGB8888,
-       DRM_FORMAT_NV12,
-};
-
 /*
  * This function is to get X or Y size shown via screen. This needs length and
  * start position of CRTC.
@@ -211,13 +205,14 @@ static void exynos_plane_attach_zpos_property(struct drm_plane *plane,
 int exynos_plane_init(struct drm_device *dev,
                      struct exynos_drm_plane *exynos_plane,
                      unsigned long possible_crtcs, enum drm_plane_type type,
+                     const uint32_t *formats, unsigned int fcount,
                      unsigned int zpos)
 {
        int err;
 
        err = drm_universal_plane_init(dev, &exynos_plane->base, possible_crtcs,
-                                      &exynos_plane_funcs, formats,
-                                      ARRAY_SIZE(formats), type);
+                                      &exynos_plane_funcs, formats, fcount,
+                                      type);
        if (err) {
                DRM_ERROR("failed to initialize plane\n");
                return err;

diff --git a/drivers/gpu/drm/exynos/exynos_drm_plane.h b/drivers/gpu/drm/exynos/exynos_drm_plane.h
index f360590d14128f2f48329a0da2cfb177a89d62bd..14b9b16a3cf80f299d88a796497140f545d2557f 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_plane.h
+++ b/drivers/gpu/drm/exynos/exynos_drm_plane.h
@@ -23,4 +23,5 @@ int exynos_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
 int exynos_plane_init(struct drm_device *dev,
                      struct exynos_drm_plane *exynos_plane,
                      unsigned long possible_crtcs, enum drm_plane_type type,
+                     const uint32_t *formats, unsigned int fcount,
                      unsigned int zpos);

diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index 7bdc5d463b1503d1e1b3d6aa8e09105c67e91186..ba249e7114332f7a555632ec4517212226138631 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -84,6 +84,12 @@ static const char fake_edid_info[] = {
        0x00, 0x00, 0x00, 0x06
 };
 
+static const uint32_t formats[] = {
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_ARGB8888,
+       DRM_FORMAT_NV12,
+};
+
 static int vidi_enable_vblank(struct exynos_drm_crtc *crtc)
 {
        struct vidi_context *ctx = crtc->ctx;
@@ -473,7 +479,8 @@ static int vidi_bind(struct device *dev, struct device *master, void *data)
                type = (zpos == ctx->default_win) ? DRM_PLANE_TYPE_PRIMARY :
                                                DRM_PLANE_TYPE_OVERLAY;
                ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
-                                       1 << ctx->pipe, type, zpos);
+                                       1 << ctx->pipe, type, formats,
+                                       ARRAY_SIZE(formats), zpos);
                if (ret)
                        return ret;
        }

diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index 4180f5f607f20bfa69e8b8de27d59a6e286456d0..b57446df3eda14cbe87d6a897bfb2a9bd0504707 100644 (file)
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -42,8 +42,8 @@
 #include "exynos_mixer.h"
 
 #define MIXER_WIN_NR           3
-#define VP_DEFAULT_WIN         2
 #define MIXER_DEFAULT_WIN      0
+#define VP_DEFAULT_WIN         2
 
 /* The pixelformats that are natively supported by the mixer. */
 #define MXR_FORMAT_RGB565      4
@@ -70,6 +70,19 @@ enum mixer_version_id {
        MXR_VER_128_0_0_184,
 };
 
+static const uint32_t mixer_formats[] = {
+       DRM_FORMAT_XRGB4444,
+       DRM_FORMAT_XRGB1555,
+       DRM_FORMAT_RGB565,
+       DRM_FORMAT_XRGB8888,
+       DRM_FORMAT_ARGB8888,
+};
+
+static const uint32_t vp_formats[] = {
+       DRM_FORMAT_NV12,
+       DRM_FORMAT_NV21,
+};
+
 struct mixer_context {
        struct platform_device *pdev;
        struct device           *dev;
@@ -1227,7 +1240,6 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data)
        struct mixer_context *ctx = dev_get_drvdata(dev);
        struct drm_device *drm_dev = data;
        struct exynos_drm_plane *exynos_plane;
-       enum drm_plane_type type;
        unsigned int zpos;
        int ret;
 
@@ -1236,12 +1248,26 @@ static int mixer_bind(struct device *dev, struct device *manager, void *data)
                return ret;
 
        for (zpos = 0; zpos < MIXER_WIN_NR; zpos++) {
+               enum drm_plane_type type;
+               const uint32_t *formats;
+               unsigned int fcount;
+
                if (zpos == VP_DEFAULT_WIN && !ctx->vp_enabled)
                        continue;
+
                type = (zpos == MIXER_DEFAULT_WIN) ? DRM_PLANE_TYPE_PRIMARY :
                                                DRM_PLANE_TYPE_OVERLAY;
+               if (zpos < VP_DEFAULT_WIN) {
+                       formats = mixer_formats;
+                       fcount = ARRAY_SIZE(mixer_formats);
+               } else {
+                       formats = vp_formats;
+                       fcount = ARRAY_SIZE(vp_formats);
+               }
+
                ret = exynos_plane_init(drm_dev, &ctx->planes[zpos],
-                                       1 << ctx->pipe, type, zpos);
+                                       1 << ctx->pipe, type, formats, fcount,
+                                       zpos);
                if (ret)
                        return ret;
        }