powerpc/mpc85xx: Add BSC9132/BSC9232 processor support

The BSC9132 is a highly integrated device that targets the evolving
 Microcell, Picocell, and Enterprise-Femto base station market subsegments.

 The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
 core technologies with MAPLE-B2P baseband acceleration processing elements
 to address the need for a high performance, low cost, integrated solution
 that handles all required processing layers without the need for an
 external device except for an RF transceiver or, in a Micro base station
 configuration, a host device that handles the L3/L4 and handover between
 sectors.

 The BSC9132 SoC includes the following function and features:
    - Power Architecture subsystem including two e500 processors with
	512-Kbyte shared L2 cache
    - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
	cache
    - 32 Kbyte of shared M3 memory
    - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
      Processing (MAPLE-B2P)
    - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
      ECC), up to 1333 MHz data rate
    - Dedicated security engine featuring trusted boot
    - Two DMA controllers
         - OCNDMA with four bidirectional channels
         - SysDMA with sixteen bidirectional channels
    - Interfaces
        - Four-lane SerDes PHY
	    - PCI Express controller complies with the PEX Specification-Rev 2.0
        - Two Common Public Radio Interface (CPRI) controller lanes
	    - High-speed USB 2.0 host and device controller with ULPI interface
        - Enhanced secure digital (SD/MMC) host controller (eSDHC)
	    - Antenna interface controller (AIC), supporting four industry
		standard JESD207/four custom ADI RF interfaces
       - ADI lanes support both full duplex FDD support & half duplex TDD
       - Universal Subscriber Identity Module (USIM) interface that
	   facilitates communication to SIM cards or Eurochip pre-paid phone
	   cards
       - Two DUART, two eSPI, and two I2C controllers
       - Integrated Flash memory controller (IFC)
       - GPIO
     - Sixteen 32-bit timers

Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 95994d3..6776c85 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -86,6 +86,7 @@ COBJS-$(CONFIG_PPC_T4240)     += ddr-gen3.o
 COBJS-$(CONFIG_PPC_B4420)      += ddr-gen3.o
 COBJS-$(CONFIG_PPC_B4860)      += ddr-gen3.o
 COBJS-$(CONFIG_BSC9131)                += ddr-gen3.o
+COBJS-$(CONFIG_BSC9132)                += ddr-gen3.o
 
 COBJS-$(CONFIG_CPM2)   += ether_fcc.o
 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
@@ -138,6 +139,7 @@ COBJS-$(CONFIG_PPC_P5040) += p5040_serdes.o
 COBJS-$(CONFIG_PPC_T4240) += t4240_serdes.o
 COBJS-$(CONFIG_PPC_B4420) += b4860_serdes.o
 COBJS-$(CONFIG_PPC_B4860) += b4860_serdes.o
+COBJS-$(CONFIG_BSC9132) += bsc9132_serdes.o
 
 COBJS-y        += cpu.o
 COBJS-y        += cpu_init.o

diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
new file mode 100644 (file)
index 0000000..300a4db
--- /dev/null
+++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c
@@ -0,0 +1,96 @@
+/*
+ * Copyright 2013 Freescale Semiconductor, Inc.
+ * Author: Prabhakar Kushwaha <prabhakar@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_serdes.h>
+
+#define SRDS1_MAX_LANES                4
+
+static u32 serdes1_prtcl_map;
+
+static u8 serdes1_cfg_tbl[][SRDS1_MAX_LANES] = {
+        [0] = {NONE, NONE, NONE, NONE},
+        [1] = {PCIE1, PCIE2, CPRI2, CPRI1},
+        [2] = {PCIE1, PCIE2, CPRI2, CPRI1},
+        [3] = {PCIE1, PCIE2, CPRI2, CPRI1},
+        [4] = {PCIE1, PCIE2, CPRI2, CPRI1},
+        [5] = {PCIE1, PCIE2, CPRI2, CPRI1},
+        [6] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+        [7] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+        [8] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+        [9] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [10] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [11] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
+       [12] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [13] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [14] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [15] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [16] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [17] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [18] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [19] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [20] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [21] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [22] = {PCIE1, PCIE2, CPRI2, CPRI1},
+       [23] = {PCIE1, PCIE2, CPRI2, CPRI1},
+       [24] = {PCIE1, PCIE2, CPRI2, CPRI1},
+       [25] = {PCIE1, PCIE2, CPRI2, CPRI1},
+       [26] = {PCIE1, PCIE2, CPRI2, CPRI1},
+       [27] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [28] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [29] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [30] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [31] = {PCIE1, PCIE2, SGMII_TSEC1, CPRI1},
+       [32] = {PCIE1, PCIE2, SGMII_TSEC1, SGMII_TSEC2},
+       [33] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [34] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [35] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [36] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [37] = {PCIE1, SGMII_TSEC2, CPRI2, CPRI1},
+       [38] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [39] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [40] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [41] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [42] = {PCIE1, SGMII_TSEC2, SGMII_TSEC1, CPRI1},
+       [43] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+       [44] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+       [45] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+       [46] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+       [47] = {SGMII_TSEC1, SGMII_TSEC2, CPRI2, CPRI1},
+};
+
+int is_serdes_configured(enum srds_prtcl prtcl)
+{
+       return (1 << prtcl) & serdes1_prtcl_map;
+}
+
+void fsl_serdes_init(void)
+{
+       ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+       u32 pordevsr = in_be32(&gur->pordevsr);
+       u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
+                               MPC85xx_PORDEVSR_IO_SEL_SHIFT;
+       int lane;
+
+       debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg);
+
+       if (srds_cfg >= ARRAY_SIZE(serdes1_cfg_tbl)) {
+               printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg);
+               return;
+       }
+
+       for (lane = 0; lane < SRDS1_MAX_LANES; lane++) {
+               enum srds_prtcl lane_prtcl = serdes1_cfg_tbl[srds_cfg][lane];
+               serdes1_prtcl_map |= (1 << lane_prtcl);
+       }
+}

diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index e8613be..ab454f5 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -86,6 +86,8 @@ static struct cpu_type cpu_type_list[] = {
        CPU_TYPE_ENTRY(B4220, B4220, 0),
        CPU_TYPE_ENTRY(BSC9130, 9130, 1),
        CPU_TYPE_ENTRY(BSC9131, 9131, 1),
+       CPU_TYPE_ENTRY(BSC9132, 9132, 2),
+       CPU_TYPE_ENTRY(BSC9232, 9232, 2),
 #elif defined(CONFIG_MPC86xx)
        CPU_TYPE_ENTRY(8610, 8610, 1),
        CPU_TYPE_ENTRY(8641, 8641, 2),

diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index f957fa3..7943fa4 100644 (file)
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -493,6 +493,21 @@
 #define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
 #define CONFIG_SYS_FSL_ERRATUM_ESDHC111
 
+#elif defined(CONFIG_BSC9132)
+#define CONFIG_MAX_CPUS                        2
+#define CONFIG_SYS_PPC_E500_DEBUG_TLB  3
+#define CONFIG_FSL_SDHC_V2_3
+#define CONFIG_SYS_FSL_NUM_LAWS                12
+#define CONFIG_TSECV2
+#define CONFIG_SYS_FSL_SEC_COMPAT      4
+#define CONFIG_NUM_DDR_CONTROLLERS     2
+#define CONFIG_SYS_CCSRBAR_DEFAULT     0xff700000
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
+#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
+#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
+#define CONFIG_SYS_FSL_PCIE_COMPAT     "fsl,qoriq-pcie-v2.2"
+
 #elif defined(CONFIG_PPC_T4240)
 #define CONFIG_SYS_PPC64               /* 64-bit core */
 #define CONFIG_FSL_CORENET             /* Freescale CoreNet platform */

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 6a818c4..67b1a44 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2150,7 +2150,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORPLLSR_DDR_RATIO     0x3e000000
 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT       25
 #else
-#ifdef CONFIG_BSC9131
+#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
 #define MPC85xx_PORPLLSR_DDR_RATIO     0x00003f00
 #else
 #define MPC85xx_PORPLLSR_DDR_RATIO     0x00003e00
@@ -2164,6 +2164,11 @@ typedef struct ccsr_gur {
        u32     porbmsr;        /* POR boot mode status */
 #define MPC85xx_PORBMSR_HA             0x00070000
 #define MPC85xx_PORBMSR_HA_SHIFT       16
+#define MPC85XX_PORBMSR_ROMLOC_SHIFT   24
+#define PORBMSR_ROMLOC_SPI     0x6
+#define PORBMSR_ROMLOC_SDHC    0x7
+#define PORBMSR_ROMLOC_NAND_2K 0x9
+#define PORBMSR_ROMLOC_NOR     0xf
        u32     porimpscr;      /* POR I/O impedance status & control */
        u32     pordevsr;       /* POR I/O device status regsiter */
 #if defined(CONFIG_P1017) || defined(CONFIG_P1023)
@@ -2188,6 +2193,9 @@ typedef struct ccsr_gur {
 #if defined(CONFIG_P1010)
 #define MPC85xx_PORDEVSR_IO_SEL                0x00600000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  21
+#elif defined(CONFIG_BSC9132)
+#define MPC85xx_PORDEVSR_IO_SEL                0x00FE0000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT  17
 #else
 #define MPC85xx_PORDEVSR_IO_SEL                0x00780000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  19
@@ -2345,6 +2353,10 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SPI1_CS3_dbg_adi2_rxen  0x00000002
 #define MPC85xx_PMUXCR_SPI1_CS3_GPO76          0x00000003
 #endif
+#ifdef CONFIG_BSC9132
+#define MPC85xx_PMUXCR0_SIM_SEL_MASK   0x0003b000
+#define MPC85xx_PMUXCR0_SIM_SEL                0x00014000
+#endif
        u32     pmuxcr2;        /* Alt. function signal multiplex control 2 */
 #if defined(CONFIG_P1010) || defined(CONFIG_P1014)
 #define MPC85xx_PMUXCR2_UART_GPIO              0x40000000
@@ -2375,6 +2387,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR2_ETSECUSB_MASK  0x001f8000
 #define MPC85xx_PMUXCR2_USB            0x00150000
 #endif
+#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
 #if defined(CONFIG_BSC9131)
 #define MPC85xx_PMUXCR2_UART_CTS_B0_SIM_PD             0X40000000
 #define MPC85xx_PMUXCR2_UART_CTS_B0_DSP_TMS            0X80000000
@@ -2418,8 +2431,9 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR2_ANT3_AGC_GPO53                 0x00000004
 #define MPC85xx_PMUXCR2_ANT3_DO_TDM                    0x00000001
 #define MPC85xx_PMUXCR2_ANT3_DO_GPIO46_49              0x00000002
+#endif
        u32     pmuxcr3;
-
+#if defined(CONFIG_BSC9131)
 #define MPC85xx_PMUXCR3_ANT3_DO4_5_TDM                 0x40000000
 #define MPC85xx_PMUXCR3_ANT3_DO4_5_GPIO_50_51          0x80000000
 #define MPC85xx_PMUXCR3_ANT3_DO6_7_TRIG_IN_SRESET_B    0x10000000
@@ -2434,6 +2448,13 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR3_SPI2_CS3_GPO94                 0x00040000
 #define MPC85xx_PMUXCR3_ANT2_AGC_RSVD                  0x00010000
 #define MPC85xx_PMUXCR3_ANT2_GPO89                     0x00030000
+#endif
+#ifdef CONFIG_BSC9132
+#define MPC85xx_PMUXCR3_USB_SEL_MASK   0x0000ff00
+#define MPC85xx_PMUXCR3_UART2_SEL      0x00005000
+#define MPC85xx_PMUXCR3_UART3_SEL_MASK 0xc0000000
+#define MPC85xx_PMUXCR3_UART3_SEL      0x40000000
+#endif
        u32 pmuxcr4;
 #else
        u8      res6[8];

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index 19fe250..8c91f08 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1113,6 +1113,8 @@
 
 #define SVR_9130       0x860001
 #define SVR_9131       0x860000
+#define SVR_9132       0x861000
+#define SVR_9232       0x861400
 
 #define SVR_Unknown    0xFFFFFF