Target specific usermode cleanup

Disable various target specific code that is only relevant to system emulation.

Signed-off-by: Paul Brook <paul@codesourcery.com>

diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
index 599938639a8c254a886511303e2541598e103604..ec2ca183d76285a0bcbc1c35f4f0e63a82778113 100644 (file)
--- a/target-microblaze/cpu.h
+++ b/target-microblaze/cpu.h
@@ -327,6 +327,8 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
     *flags = env->iflags & IFLAGS_TB_MASK;
 }
 
+#if !defined(CONFIG_USER_ONLY)
 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                           int is_asi, int size);
 #endif
+#endif

diff --git a/target-microblaze/op_helper.c b/target-microblaze/op_helper.c
index 8a9cea2f270781c9acff3117361c15b5d5a53526..be0c829735d4ec68a4fc2206969b93ae3016c0e8 100644 (file)
--- a/target-microblaze/op_helper.c
+++ b/target-microblaze/op_helper.c
@@ -245,7 +245,6 @@ void helper_mmu_write(uint32_t rn, uint32_t v)
 {
     mmu_write(env, rn, v);
 }
-#endif
 
 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                           int is_asi, int size)
@@ -282,3 +281,4 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
     }
     env = saved_env;
 }
+#endif

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 8291bf9b0a217b1e06be95e8ef928f524fe814e9..7285636b68f32c3c954796bd5641523d8f91e55d 100644 (file)
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -36,6 +36,7 @@ struct r4k_tlb_t {
     target_ulong PFN[2];
 };
 
+#if !defined(CONFIG_USER_ONLY)
 typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
 struct CPUMIPSTLBContext {
     uint32_t nb_tlb;
@@ -51,6 +52,7 @@ struct CPUMIPSTLBContext {
         } r4k;
     } mmu;
 };
+#endif
 
 typedef union fpr_t fpr_t;
 union fpr_t {
@@ -468,13 +470,16 @@ struct CPUMIPSState {
     CPU_COMMON
 
     CPUMIPSMVPContext *mvp;
+#if !defined(CONFIG_USER_ONLY)
     CPUMIPSTLBContext *tlb;
+#endif
 
     const mips_def_t *cpu_model;
     void *irq[8];
     struct QEMUTimer *timer; /* Internal timer */
 };
 
+#if !defined(CONFIG_USER_ONLY)
 int no_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
                         target_ulong address, int rw, int access_type);
 int fixed_mmu_map_address (CPUMIPSState *env, target_phys_addr_t *physical, int *prot,
@@ -485,10 +490,12 @@ void r4k_helper_tlbwi (void);
 void r4k_helper_tlbwr (void);
 void r4k_helper_tlbp (void);
 void r4k_helper_tlbr (void);
-void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 
 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                           int unused, int size);
+#endif
+
+void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 
 #define cpu_init cpu_mips_init
 #define cpu_exec cpu_mips_exec
@@ -598,9 +605,11 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
                                int mmu_idx, int is_softmmu);
 #define cpu_handle_mmu_fault cpu_mips_handle_mmu_fault
 void do_interrupt (CPUState *env);
+#if !defined(CONFIG_USER_ONLY)
 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra);
 target_phys_addr_t cpu_mips_translate_address (CPUState *env, target_ulong address,
                                               int rw);
+#endif
 
 static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
 {

diff --git a/target-mips/helper.c b/target-mips/helper.c
index 43d11b351ddb634c13538364784d2c935a7246f3..933c7bc1dfb12f5b11319c6d1e76c878ee68359b 100644 (file)
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -34,6 +34,8 @@ enum {
     TLBRET_MATCH = 0
 };
 
+#if !defined(CONFIG_USER_ONLY)
+
 /* no MMU emulation */
 int no_mmu_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
                         target_ulong address, int rw, int access_type)
@@ -98,7 +100,6 @@ int r4k_map_address (CPUState *env, target_phys_addr_t *physical, int *prot,
     return TLBRET_NOMATCH;
 }
 
-#if !defined(CONFIG_USER_ONLY)
 static int get_physical_address (CPUState *env, target_phys_addr_t *physical,
                                 int *prot, target_ulong address,
                                 int rw, int access_type)
@@ -599,6 +600,7 @@ void do_interrupt (CPUState *env)
     env->exception_index = EXCP_NONE;
 }
 
+#if !defined(CONFIG_USER_ONLY)
 void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
 {
     r4k_tlb_t *tlb;
@@ -652,3 +654,4 @@ void r4k_invalidate_tlb (CPUState *env, int idx, int use_extra)
         }
     }
 }
+#endif

diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index cecc6e2cd56f0f6cf60ff44168364cae38e1e7a0..2ad44867278879755b2718997ab7a2ec2d3fe074 100644 (file)
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -332,6 +332,7 @@ union ppc_avr_t {
     uint64_t u64[2];
 };
 
+#if !defined(CONFIG_USER_ONLY)
 /* Software TLB cache */
 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
 struct ppc6xx_tlb_t {
@@ -354,6 +355,7 @@ union ppc_tlb_t {
     ppc6xx_tlb_t tlb6;
     ppcemb_tlb_t tlbe;
 };
+#endif
 
 typedef struct ppc_slb_t ppc_slb_t;
 struct ppc_slb_t {
@@ -699,6 +701,7 @@ struct CPUPPCState {
     int (*osi_call)(struct CPUPPCState *env);
 };
 
+#if !defined(CONFIG_USER_ONLY)
 /* Context used internally during MMU translations */
 typedef struct mmu_ctx_t mmu_ctx_t;
 struct mmu_ctx_t {
@@ -710,6 +713,7 @@ struct mmu_ctx_t {
     int key;                       /* Access key                */
     int nx;                        /* Non-execute area          */
 };
+#endif
 
 /*****************************************************************************/
 CPUPPCState *cpu_ppc_init (const char *cpu_model);
@@ -724,8 +728,10 @@ int cpu_ppc_signal_handler (int host_signum, void *pinfo,
 int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw,
                               int mmu_idx, int is_softmmu);
 #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault
+#if !defined(CONFIG_USER_ONLY)
 int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr,
                           int rw, int access_type);
+#endif
 void do_interrupt (CPUPPCState *env);
 void ppc_hw_interrupt (CPUPPCState *env);
 

diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
index 18a55320f4c68d300e71fbe1c748977e8868157b..f8b1680296afa66b6cafc3e64ddb893bef28b0fc 100644 (file)
--- a/target-sh4/cpu.h
+++ b/target-sh4/cpu.h
@@ -169,9 +169,11 @@ int cpu_sh4_handle_mmu_fault(CPUSH4State * env, target_ulong address, int rw,
 void do_interrupt(CPUSH4State * env);
 
 void sh4_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
+#if !defined(CONFIG_USER_ONLY)
 void cpu_sh4_invalidate_tlb(CPUSH4State *s);
 void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, target_phys_addr_t addr,
                                    uint32_t mem_value);
+#endif
 
 int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr);
 

diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 0c5a7ef54d1eb350d1224c9093d79c4a194d515c..580f4d46c8c20ab4ece681bbeda2b72a64658f77 100644 (file)
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -550,8 +550,10 @@ static inline void PUT_CWP64(CPUSPARCState *env1, int cwp)
 #endif
 
 /* cpu-exec.c */
+#if !defined(CONFIG_USER_ONLY)
 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                           int is_asi, int size);
+#endif
 int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 
 #define cpu_init cpu_sparc_init

diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c
index eb4f5a4338035277888f3a23c388c7676c1dab7c..704631a24e8e65b7ca6a854b8f7cfba8f624571e 100644 (file)
--- a/target-sparc/op_helper.c
+++ b/target-sparc/op_helper.c
@@ -47,6 +47,11 @@
 #endif
 #endif
 
+#if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
+static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
+                          int is_asi, int size);
+#endif
+
 #if defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
 // Calculates TSB pointer value for fault page size 8k or 64k
 static uint64_t ultrasparc_tsb_pointer(uint64_t tsb_register,
@@ -3707,9 +3712,10 @@ void tlb_fill(target_ulong addr, int is_write, int mmu_idx, void *retaddr)
     env = saved_env;
 }
 
-#endif
+#endif /* !CONFIG_USER_ONLY */
 
 #ifndef TARGET_SPARC64
+#if !defined(CONFIG_USER_ONLY)
 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                           int is_asi, int size)
 {
@@ -3770,9 +3776,15 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 
     env = saved_env;
 }
+#endif
+#else
+#if defined(CONFIG_USER_ONLY)
+static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
+                          int is_asi, int size)
 #else
 void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
                           int is_asi, int size)
+#endif
 {
     CPUState *saved_env;
 
@@ -3795,6 +3807,7 @@ void do_unassigned_access(target_phys_addr_t addr, int is_write, int is_exec,
 }
 #endif
 
+
 #ifdef TARGET_SPARC64
 void helper_tick_set_count(void *opaque, uint64_t count)
 {