drm/amdgpu: Replace numbers with PCI_EXP_LNKCTL2 definitions

Replace hard-coded magic numbers with the descriptive PCI_EXP_LNKCTL2
definitions.  No functional change intended.

Link: https://lore.kernel.org/r/20191112173503.176611-4-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index 13a5696..3067bb8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1498,13 +1498,19 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
 
                                /* linkctl2 */
                                pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 7));
-                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN);
+                               tmp16 |= (bridge_cfg2 &
+                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN));
                                pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 7));
-                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN);
+                               tmp16 |= (gpu_cfg2 &
+                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN));
                                pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                tmp = RREG32_PCIE(ixPCIE_LC_CNTL4);
@@ -1521,13 +1527,13 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev)
        WREG32_PCIE(ixPCIE_LC_SPEED_CNTL, speed_cntl);
 
        pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-       tmp16 &= ~0xf;
+       tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
        if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-               tmp16 |= 3; /* gen3 */
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
        else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-               tmp16 |= 2; /* gen2 */
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
        else
-               tmp16 |= 1; /* gen1 */
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
        pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
        speed_cntl = RREG32_PCIE(ixPCIE_LC_SPEED_CNTL);

diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c
index 1e35017..a7dcb0d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si.c
+++ b/drivers/gpu/drm/amd/amdgpu/si.c
@@ -1737,13 +1737,19 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
                                pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL, tmp16);
 
                                pci_read_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 7));
-                               tmp16 |= (bridge_cfg2 & ((1 << 4) | (7 << 7)));
+                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN);
+                               tmp16 |= (bridge_cfg2 &
+                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN));
                                pci_write_config_word(root, bridge_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-                               tmp16 &= ~((1 << 4) | (7 << 7));
-                               tmp16 |= (gpu_cfg2 & ((1 << 4) | (7 << 7)));
+                               tmp16 &= ~(PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN);
+                               tmp16 |= (gpu_cfg2 &
+                                         (PCI_EXP_LNKCTL2_ENTER_COMP |
+                                          PCI_EXP_LNKCTL2_TX_MARGIN));
                                pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
                                tmp = RREG32_PCIE_PORT(PCIE_LC_CNTL4);
@@ -1758,13 +1764,13 @@ static void si_pcie_gen3_enable(struct amdgpu_device *adev)
        WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
 
        pci_read_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16);
-       tmp16 &= ~0xf;
+       tmp16 &= ~PCI_EXP_LNKCTL2_TLS;
        if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
-               tmp16 |= 3;
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_8_0GT; /* gen3 */
        else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
-               tmp16 |= 2;
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_5_0GT; /* gen2 */
        else
-               tmp16 |= 1;
+               tmp16 |= PCI_EXP_LNKCTL2_TLS_2_5GT; /* gen1 */
        pci_write_config_word(adev->pdev, gpu_pos + PCI_EXP_LNKCTL2, tmp16);
 
        speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);