Fix target-customized spilling in the register scavenger

This is a follow-up to r178073 (which should actually make target-customized
spilling work again).

I still don't have a regression test for this (but it would be good to have
one; Thumb 1 and Mips16 use this callback as well).

Patch by Richard Sandiford.

llvm-svn: 178137

diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index 6b85cd9..55a66ba 100644 (file)
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -371,7 +371,7 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
     if (Scavenged[SI].Reg == 0)
       break;
 
-  if (SI < Scavenged.size()) {
+  if (SI == Scavenged.size()) {
     // We need to scavenge a register but have no spill slot, the target
     // must know how to do it (if not, we'll assert below).
     Scavenged.push_back(ScavengedInfo());