#include <common.h>
#include <cpu_func.h>
-__weak void reset_cpu(ulong addr)
+__weak void reset_cpu(void)
{
/* Stop debug session here */
__builtin_arc_brk();
{
printf("Resetting the board...\n");
- reset_cpu(0);
+ reset_cpu();
return 0;
}
#include <asm/io.h>
/* We reset the CPU by generating a 1-->0 transition on DeviceCfg bit 31. */
-extern void reset_cpu(ulong addr)
+extern void reset_cpu(void)
{
struct syscon_regs *syscon = (struct syscon_regs *)SYSCON_BASE;
uint32_t value;
/*
* Reset the cpu by setting up the watchdog timer and let him time out
*/
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
/* Disable watchdog and set Time-Out field to 0 */
WCR = 0x00000000;
* 2. Write key value to TMP_WSAR reg.
* 3. Perform write operation.
*/
-void reset_cpu(unsigned long ignored)
+void reset_cpu(void)
{
struct armd1mpmu_registers *mpmu =
(struct armd1mpmu_registers *) ARMD1_MPMU_BASE;
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
/*
* Reset the cpu by setting up the watchdog timer and let it time out
*/
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
struct wdog_regs *regs = (struct wdog_regs *)IMX_WDT_BASE;
/* Disable watchdog and set Time-Out field to 0 */
/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
__weak void lowlevel_init(void) {}
-void reset_cpu(ulong ignored) __attribute__((noreturn));
+void reset_cpu(void) __attribute__((noreturn));
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
struct mxs_rtc_regs *rtc_regs =
(struct mxs_rtc_regs *)MXS_RTC_BASE;
#include <asm/arch/spr_syscntl.h>
#include <linux/delay.h>
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
struct syscntl_regs *syscntl_regs_p =
(struct syscntl_regs *)CONFIG_SPEAR_SYSCNTLBASE;
#ifndef CONFIG_ARCH_INTEGRATOR
-__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
+__attribute__((noreturn)) void reset_cpu(void)
{
writew(0x0, 0xfffece10);
writew(0x8, 0xfffece10);
#define CLKS_SHIFT 20 /* Clock period shift */
#define LD_SHIFT 0 /* Reload value shift */
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
/*
* Set WD enable, RST enable,
#define CRMU_MAIL_BOX1 0x03024028
#define CRMU_SOFT_RESET_CMD 0xFFFFFFFF
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
/* Send soft reset command via Mailbox. */
writel(CRMU_SOFT_RESET_CMD, CRMU_MAIL_BOX1);
#define CRU_RESET_OFFSET 0x1803F184
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
/* Reset the cpu by setting software reset request bit */
writel(0x1, CRU_RESET_OFFSET);
}
#endif
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
}
#endif
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
void *clkpwr_reg = (void *)PHY_BASEADDR_CLKPWR;
const u32 sw_rst_enb_bitpos = 3;
#include <asm/io.h>
#include <asm/arch/stv0991_wdru.h>
#include <linux/delay.h>
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
puts("System is going to reboot ...\n");
/*
/*
* Perform the low-level reset.
*/
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
/*
* Perform reset but keep priority group unchanged.
__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR;
-void __efi_runtime reset_cpu(ulong addr)
+void __efi_runtime reset_cpu(void)
{
#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A)
/* clear the RST_REQ_MSK and SW_RST_REQ */
case EFI_RESET_COLD:
case EFI_RESET_WARM:
case EFI_RESET_PLATFORM_SPECIFIC:
- reset_cpu(0);
+ reset_cpu();
break;
case EFI_RESET_SHUTDOWN:
/* Nothing we can do */
#define SRC_SCR_SW_RST (1<<12)
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
printf("Feature not supported.\n");
};
writel(readl(CKEN) | CKEN14_I2C, CKEN);
}
-void __attribute__((weak)) reset_cpu(ulong ignored) __attribute__((noreturn));
+void __attribute__((weak)) reset_cpu(void) __attribute__((noreturn));
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
uint32_t tmp;
#define RSRR 0x00
#define RCSR 0x04
-__attribute__((noreturn)) void reset_cpu(ulong addr __attribute__((unused)))
+__attribute__((noreturn)) void reset_cpu(void)
{
/* repeat endlessly */
while (1) {
void bad_mode (void)
{
panic ("Resetting CPU ...\n");
- reset_cpu(0);
+ reset_cpu();
}
static void show_efi_loaded_images(struct pt_regs *regs)
void bad_mode(void)
{
panic("Resetting CPU ...\n");
- reset_cpu(0);
+ reset_cpu();
}
void do_hard_fault(struct autosave_regs *autosave_regs)
disable_interrupts();
reset_misc();
- reset_cpu(0);
+ reset_cpu();
/*NOTREACHED*/
return 0;
/* true empty function for defining weak symbol */
}
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
at91_st_t *st = (at91_st_t *) ATMEL_BASE_ST;
#include <asm/arch/at91_rstc.h>
/* Reset the cpu by telling the reset controller to do so */
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
at91_rstc_t *rstc = (at91_rstc_t *) ATMEL_BASE_RSTC;
#include <asm/arch/at91_rstc.h>
/* Reset the cpu by telling the reset controller to do so */
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
at91_rstc_t *rstc = (at91_rstc_t *)ATMEL_BASE_RSTC;
writel(BCM2835_WDOG_PASSWORD | rstc, &wdog_regs->rstc);
}
-void reset_cpu(ulong ticks)
+void reset_cpu(void)
{
struct bcm2835_wdog_regs *regs =
(struct bcm2835_wdog_regs *)BCM2835_WDOG_PHYSADDR;
#include <asm/arch/timer_defs.h>
#include <asm/arch/hardware.h>
-void reset_cpu(unsigned long a)
+void reset_cpu(void)
{
struct davinci_timer *const wdttimer =
(struct davinci_timer *)DAVINCI_WDOG_BASE;
void *secondary_boot_addr = (void *)_main;
#endif /* CONFIG_TARGET_ESPRESSO7420 */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
#ifdef CONFIG_CPU_V7A
writel(0x1, samsung_get_base_swreset());
#endif
#if !CONFIG_IS_ENABLED(SYSRESET)
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
#endif
#ifndef CONFIG_ULP_WATCHDOG
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
setbits_le32(SIM0_RBASE, SIM_SOPT1_A7_SW_RESET);
while (1)
#endif
#ifndef CONFIG_SYSRESET
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
}
#endif
if (!ecc_test) {
puts("Reseting the device ...\n");
- reset_cpu(0);
+ reset_cpu();
}
}
tmp &= ~KS2_RSTYPE_PLL_SOFT;
__raw_writel(tmp, KS2_RSTCTRL_RSCFG);
- reset_cpu(0);
+ reset_cpu();
}
}
#endif
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
volatile u32 *rstctrl = (volatile u32 *)(KS2_RSTCTRL);
u32 tmp;
#include <asm/arch/soc.h>
#include <mvebu_mmc.h>
-void reset_cpu(unsigned long ignored)
+void reset_cpu(void)
{
struct kwcpu_registers *cpureg =
(struct kwcpu_registers *)KW_CPU_REG_BASE;
static struct clk_pm_regs *clk = (struct clk_pm_regs *)CLK_PM_BASE;
static struct wdt_regs *wdt = (struct wdt_regs *)WDT_BASE;
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
/* Enable watchdog clock */
setbits_le32(&clk->timclk_ctrl, CLK_TIMCLK_WATCHDOG);
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
psci_system_reset();
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct udevice *watchdog_dev = NULL;
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
psci_system_reset();
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
psci_system_reset();
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct pt_regs regs;
;
}
#else
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
psci_system_reset();
}
return fdt_setprop_inplace(blob, node, "ranges", new_ranges, len);
}
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
/*
* Write magic number of 0x1d1e to North Bridge Warm Reset register
dcache_enable();
}
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
u32 reg;
*/
}
-void reset_cpu(unsigned long ignored)
+void reset_cpu(void)
{
struct mvebu_system_registers *reg =
(struct mvebu_system_registers *)MVEBU_SYSTEM_REG_BASE;
return 0x80000;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
return 0x80000;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
die_id[3] = readl((*ctrl)->control_std_fuse_die_id_3);
}
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
u32 omap_rev = omap_revision();
#include <asm/arch/cpu.h>
#include <linux/compiler.h>
-void __weak reset_cpu(unsigned long ignored)
+void __weak reset_cpu(void)
{
writel(PRM_RSTCTRL_RESET, PRM_RSTCTRL);
}
#define BUFLEN 16
-void reset_cpu(unsigned long ignored)
+void reset_cpu(void)
{
struct orion5x_cpu_registers *cpureg =
(struct orion5x_cpu_registers *)ORION5X_CPU_REG_BASE;
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
psci_system_reset();
}
phys_addr_t socfpga_get_rstmgr_addr(void);
-void reset_cpu(ulong addr);
+void reset_cpu(void);
void socfpga_per_reset(u32 reset, int set);
void socfpga_per_reset_all(void);
}
#endif
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
static const struct sunxi_wdog *wdog =
tegra_pmc_writel(2, PMC_SCRATCH0);
disable_interrupts();
- reset_cpu(0);
+ reset_cpu();
return 0;
}
writel(value, NV_PA_PMC_BASE + offset);
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
u32 value;
void __secure psci_system_reset(void)
{
- reset_cpu(0);
+ reset_cpu();
}
#define __SECURE
#endif
-void __SECURE reset_cpu(unsigned long ignored)
+void __SECURE reset_cpu(void)
{
u32 tmp;
>> ZYNQ_SILICON_VER_SHIFT;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
zynq_slcr_cpu_reset();
while (1)
/*
* Perform the low-level reset.
*/
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
while (1)
;
/*
* reset to the base addr of andesboot.
* currently no ROM loader at addr 0.
- * do not use reset_cpu(0);
+ * do not use reset_cpu();
*/
#ifdef CONFIG_FTWDT010_WATCHDOG
/*
void bad_mode(void)
{
panic("Resetting CPU ...\n");
- reset_cpu(0);
+ reset_cpu();
}
void show_regs(struct pt_regs *regs)
* We don't want to include common.h in this file since it uses
* system headers. So add a declation here.
*/
- extern void reset_cpu(unsigned long addr);
+ extern void reset_cpu(void);
SDL_Event event;
while (SDL_PollEvent(&event)) {
switch (event.type) {
case SDL_QUIT:
puts("LCD window closed - quitting\n");
- reset_cpu(1);
+ reset_cpu();
break;
}
}
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
disable_interrupts();
- reset_cpu(0);
+ reset_cpu();
return 0;
}
}
#endif
-void reset_cpu(unsigned long ignored)
+void reset_cpu(void)
{
/* Address error with SR.BL=1 first. */
trigger_address_error();
/* System is not happy after keyboard reset... */
debug("Issuing CF9 warm reset\n");
- reset_cpu(0);
+ reset_cpu();
}
ret = cpu_common_init();
spl_dram_init();
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
#endif /* CONFIG_SPL_BUILD */
#include <netdev.h>
#include <asm/io.h>
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
#define CRM_SWRESET 0xff101044
writel(0x1, (void *)CRM_SWRESET);
/*
* Board specific reset that is system reset.
*/
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
/* TODO */
}
}
/* Nothing to be done here as handled by PSCI interface */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
}
/* Use the ARM Watchdog System to cause reset */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
if (v2m_cfg_write(SYS_CFG_REBOOT | SYS_CFG_SITE_MB, 0))
printf("Unable to reboot\n");
#endif
/* Actual reset is done via PSCI. */
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
#define RST_CA57RESCNT (RST_BASE + 0x40)
#define RST_CODE 0xA5A5000F
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
writel(RST_CODE, RST_CA57RESCNT);
}
printf("Resetting ...\n");
writel(RESET_MASK, GPIO1_BASE + OMAP_GPIO_IRQSTATUS_SET_0);
disable_interrupts();
- reset_cpu(0);
+ reset_cpu();
/*NOTREACHED*/
}
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
psci_system_reset();
}
return BCM_NS3_MEM_END;
}
-void reset_cpu(ulong level)
+void reset_cpu(void)
{
/* Perform a level 3 reset */
psci_system_reset2(3, 0);
return 0;
}
-void reset_cpu(ulong ignored)
+void reset_cpu(void)
{
}
/*
* Board specific reset that is system reset.
*/
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
break;
default:
puts("Failed configuring DRAM, resetting...\n\n");
- reset_cpu(0);
+ reset_cpu();
}
debug("%s: setting DRAM size to %ldM\n", __func__, size >> 20);
config_ddr(303, &ioregs, &ddr3_data,
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
invoke_psci_fn_smc(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
}
/*
* Board specific reset that is system reset.
*/
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
/* TODO */
}
/*
* Board specific reset that is system reset.
*/
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
/* TODO */
}
is_cpu_type(MXC_CPU_MX6SL)) {
printf("cpu type 0x%x doesn't support 64-bit bus\n",
get_cpu_type());
- reset_cpu(0);
+ reset_cpu();
}
}
#ifdef CONFIG_MX6SL
return 1024;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
return (midr & 0xfff0) == 0xc090;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
writel(HB_PWR_HARD_RESET, HB_SREG_A9_PWR_REQ);
if (is_highbank())
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
writel(0x48698284, &ao_sc->stat0);
wfi();
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
psci_system_reset();
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
psci_system_reset();
}
return ret;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
/* Soft Power On Reset */
writel((1 << 31), RESCNT2);
#endif
}
-void reset_cpu(ulong addr) {}
+void reset_cpu(void) {}
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct arm_smccc_res res;
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
psci_system_reset();
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
psci_system_reset();
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct udevice *dev;
const u8 pmic_bus = 7;
spl_boot_list[2] = BOOT_DEVICE_NONE;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct udevice *dev;
const u8 pmic_bus = 6;
#define RST_CA57_CODE 0xA5A5000F
#define RST_CA53_CODE 0x5A5A000F
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
unsigned long midr, cputype;
#define RST_CA53RESCNT (RST_BASE + 0x44)
#define RST_CA53_CODE 0x5A5A000F
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
writel(RST_CA53_CODE, RST_CA53RESCNT);
}
#define RST_CA57_CODE 0xA5A5000F
#define RST_CA53_CODE 0x5A5A000F
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
unsigned long midr, cputype;
#define RST_CA53RESCNT (RST_BASE + 0x44)
#define RST_CA53_CODE 0x5A5A000F
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
writel(RST_CA53_CODE, RST_CA53RESCNT);
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct udevice *dev;
const u8 pmic_bus = 6;
spl_boot_list[2] = BOOT_DEVICE_NONE;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
/* Dummy read (must read WRCSR:WOVF at least once before clearing) */
readb(RZA1_WDT_BASE + WRCSR);
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct udevice *dev;
const u8 pmic_bus = 6;
spl_boot_list[2] = BOOT_DEVICE_NONE;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct udevice *dev;
const u8 pmic_bus = 2;
spl_boot_list[2] = BOOT_DEVICE_NONE;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct udevice *dev;
const u8 pmic_bus = 6;
spl_boot_list[2] = BOOT_DEVICE_NONE;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
{
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
#define RST_RSTOUTCR (RST_BASE + 0x58)
#define RST_CODE 0xA5A5000F
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_SH)
i2c_reg_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x20, 0x80);
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct udevice *dev;
const u8 pmic_bus = 1;
spl_boot_list[2] = BOOT_DEVICE_NONE;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
"cpld write addr val\n"
);
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
cpld_write(CPLD_ADDR_RESET, 1);
}
spl_boot_list[2] = BOOT_DEVICE_NONE;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
/* Bits in CREG_BOOT register */
#define CREG_BOOT_WP_BIT BIT(8)
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
writel(1, CREG_IP_SW_RESET);
while (1)
#define IOTDK_RESET_SEQ 0x55AA6699
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
writel(IOTDK_RESET_SEQ, RESET_REG);
}
board_init_r(NULL, 0);
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
board_init_r(NULL, 0);
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
/*
* Board specific reset that is system reset.
*/
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
/* TODO */
}
/*
* Board specific reset that is system reset.
*/
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
/* TODO */
}
}
#endif
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
/*
* Board specific reset that is system reset.
*/
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
/* TODO */
}
board_init_r(NULL, 0);
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct udevice *dev;
/*
* Board specific reset that is system reset.
*/
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
return 0;
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
}
#endif
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
}
#define reboot() do { \
printf("\trebooting...\n"); \
- reset_cpu(0); \
+ reset_cpu(); \
} while (0)
static int test_fast_enable(struct udevice *dev)
/**
* reset_cpu() - calls sysreset_walk(SYSRESET_WARM)
*/
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
sysreset_walk_halt(SYSRESET_WARM);
}
#if !defined(CONFIG_IMX_WATCHDOG) || \
(defined(CONFIG_IMX_WATCHDOG) && !CONFIG_IS_ENABLED(WDT))
-void __attribute__((weak)) reset_cpu(ulong addr)
+void __attribute__((weak)) reset_cpu(void)
{
struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
hw_watchdog_reset();
}
-void reset_cpu(ulong addr)
+void reset_cpu(void)
{
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
*/
int cleanup_before_linux_select(int flags);
-void reset_cpu(ulong addr);
-;
+void reset_cpu(void);
+
#endif
/**
* reset_cpu() - calls sysreset_walk(SYSRESET_WARM)
*/
-void reset_cpu(ulong addr);
+void reset_cpu(void);
#endif
projects / platform / kernel / u-boot.git / commitdiff