drm/rockchip: vop2: Fix eDP/HDMI sync polarities

The hsync/vsync polarities were not honoured for the eDP and HDMI ports.
Add the register settings to configure the polarities as requested by the
DRM_MODE_FLAG_PHSYNC/DRM_MODE_FLAG_PVSYNC flags.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Fixes: 604be85547ce ("drm/rockchip: Add VOP2 driver")
Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20220815133942.4051532-1-s.hauer@pengutronix.de

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
index e4631f5..f9aa8b9 100644 (file)
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
@@ -1439,11 +1439,15 @@ static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id,
                die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX;
                die |= RK3568_SYS_DSP_INFACE_EN_HDMI |
                           FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id);
+               dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL;
+               dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags);
                break;
        case ROCKCHIP_VOP2_EP_EDP0:
                die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX;
                die |= RK3568_SYS_DSP_INFACE_EN_EDP |
                           FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id);
+               dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL;
+               dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags);
                break;
        case ROCKCHIP_VOP2_EP_MIPI0:
                die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX;