i386: Remove constraints when used with constant integer predicates, take 2

const_int_operand and other const*_operand predicates do not need
constraints when the constraint is inherited from the range of
constant integer predicate.  Remove the constraint in case all
alternatives use the same inherited constraint.

However, when there are operands, commitative with a non-constant
operand, the operand effectively matches e.g.
nonimmediate_operand|const_int_operand rather than just
const_int_operand.  We should keep the constraint for
const_int_operand that are in a % pair. See PR 105624.

2022-05-30  Uroš Bizjak  <ubizjak@gmail.com>

gcc/ChangeLog:

	* config/i386/i386.md: Remove constraints when used with
	const_int_operand, const0_operand, const_1_operand, constm1_operand,
	const8_operand, const128_operand, const248_operand, const123_operand,
	const2367_operand, const1248_operand, const359_operand,
	const_4_or_8_to_11_operand, const48_operand, const_0_to_1_operand,
	const_0_to_3_operand, const_0_to_4_operand, const_0_to_5_operand,
	const_0_to_7_operand, const_0_to_15_operand, const_0_to_31_operand,
	const_0_to_63_operand, const_0_to_127_operand, const_0_to_255_operand,
	const_0_to_255_mul_8_operand, const_1_to_31_operand,
	const_1_to_63_operand, const_2_to_3_operand, const_4_to_5_operand,
	const_4_to_7_operand, const_6_to_7_operand, const_8_to_9_operand,
	const_8_to_11_operand, const_8_to_15_operand, const_10_to_11_operand,
	const_12_to_13_operand, const_12_to_15_operand, const_14_to_15_operand,
	const_16_to_19_operand, const_16_to_31_operand, const_20_to_23_operand,
	const_24_to_27_operand and const_28_to_31_operand.
	* config/i386/mmx.md: Ditto.
	* config/i386/sse.md: Ditto.
	* config/i386/subst.md: Ditto.
	* config/i386/sync.md: Ditto.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/pr105624.c: New test.

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 17bdbd9..d070ccd 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -6298,7 +6298,7 @@
   [(set (reg FLAGS_REG)
        (compare
          (match_operand:SWI124 1 "nonimmediate_operand" "0")
-         (match_operand:SWI124 2 "const_int_operand" "n")))
+         (match_operand:SWI124 2 "const_int_operand")))
    (clobber (match_scratch:SWI124 0 "=<r>"))]
   "ix86_match_ccmode (insn, CCGCmode)"
 {
@@ -6504,7 +6504,7 @@
        (eq:CCO (plus:<DWI>
                   (sign_extend:<DWI>
                      (match_operand:SWI 1 "nonimmediate_operand" "0"))
-                  (match_operand:<DWI> 3 "const_int_operand" "i"))
+                  (match_operand:<DWI> 3 "const_int_operand"))
                (sign_extend:<DWI>
                   (plus:SWI
                     (match_dup 1)
@@ -6577,7 +6577,7 @@
          (plus:<QPWI>
            (sign_extend:<QPWI>
              (match_operand:<DWI> 1 "nonimmediate_operand" "%0"))
-           (match_operand:<QPWI> 3 "const_scalar_int_operand" ""))
+           (match_operand:<QPWI> 3 "const_scalar_int_operand" "n"))
          (sign_extend:<QPWI>
            (plus:<DWI>
              (match_dup 1)
@@ -6662,7 +6662,7 @@
                [(match_operand 3 "flags_reg_operand") (const_int 0)])
              (sign_extend:<DWI>
                (match_operand:SWI 1 "nonimmediate_operand" "%0")))
-           (match_operand:<DWI> 6 "const_int_operand" ""))
+           (match_operand:<DWI> 6 "const_int_operand" "n"))
          (sign_extend:<DWI>
            (plus:SWI
              (plus:SWI
@@ -6827,8 +6827,8 @@
        (any_or:SWI12
          (ashift:SWI12
            (match_operand:SWI12 1 "index_register_operand" "l")
-           (match_operand 2 "const_0_to_3_operand" "n"))
-         (match_operand 3 "const_int_operand" "n")))]
+           (match_operand 2 "const_0_to_3_operand"))
+         (match_operand 3 "const_int_operand")))]
   "(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
    && ((unsigned HOST_WIDE_INT) INTVAL (operands[3])
        < (HOST_WIDE_INT_1U << INTVAL (operands[2])))"
@@ -6851,8 +6851,8 @@
        (any_or:SWI48
          (ashift:SWI48
            (match_operand:SWI48 1 "index_register_operand" "l")
-           (match_operand 2 "const_0_to_3_operand" "n"))
-         (match_operand 3 "const_int_operand" "n")))]
+           (match_operand 2 "const_0_to_3_operand"))
+         (match_operand 3 "const_int_operand")))]
   "(unsigned HOST_WIDE_INT) INTVAL (operands[3])
    < (HOST_WIDE_INT_1U << INTVAL (operands[2]))"
   "#"
@@ -7048,7 +7048,7 @@
        (eq:CCO (minus:<DWI>
                   (sign_extend:<DWI>
                      (match_operand:SWI 1 "nonimmediate_operand" "0"))
-                  (match_operand:<DWI> 3 "const_int_operand" "i"))
+                  (match_operand:<DWI> 3 "const_int_operand"))
                (sign_extend:<DWI>
                   (minus:SWI
                     (match_dup 1)
@@ -7116,7 +7116,7 @@
          (minus:<QPWI>
            (sign_extend:<QPWI>
              (match_operand:<DWI> 1 "nonimmediate_operand" "0"))
-           (match_operand:<QPWI> 3 "const_scalar_int_operand" ""))
+           (match_operand:<QPWI> 3 "const_scalar_int_operand"))
          (sign_extend:<QPWI>
            (minus:<DWI>
              (match_dup 1)
@@ -7199,7 +7199,7 @@
                (match_operand:SWI 1 "nonimmediate_operand" "%0"))
              (match_operator:<DWI> 4 "ix86_carry_flag_operator"
                [(match_operand 3 "flags_reg_operand") (const_int 0)]))
-           (match_operand:<DWI> 6 "const_int_operand" ""))
+           (match_operand:<DWI> 6 "const_int_operand" "n"))
          (sign_extend:<DWI>
            (minus:SWI
              (minus:SWI
@@ -7469,7 +7469,7 @@
                (match_operand:SWI48 1 "nonimmediate_operand" "%0"))
              (match_operand:SWI48 2 "x86_64_immediate_operand" "e")))
          (plus:<DWI>
-           (match_operand:<DWI> 6 "const_scalar_int_operand" "")
+           (match_operand:<DWI> 6 "const_scalar_int_operand")
            (match_operator:<DWI> 4 "ix86_carry_flag_operator"
              [(match_dup 3) (const_int 0)]))))
    (set (match_operand:SWI48 0 "nonimmediate_operand" "=rm")
@@ -8463,7 +8463,7 @@
          (lshiftrt:<DWI>
            (mult:<DWI> (zero_extend:<DWI> (match_dup 2))
                        (zero_extend:<DWI> (match_dup 3)))
-           (match_operand:QI 4 "const_int_operand" "n"))))]
+           (match_operand:QI 4 "const_int_operand"))))]
   "TARGET_BMI2 && INTVAL (operands[4]) == <MODE_SIZE> * BITS_PER_UNIT
    && !(MEM_P (operands[2]) && MEM_P (operands[3]))"
   "mulx\t{%3, %0, %1|%1, %0, %3}"
@@ -9097,7 +9097,7 @@
 (define_insn_and_split "*udivmod<mode>4_pow2"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
        (udiv:SWI48 (match_operand:SWI48 2 "register_operand" "0")
-                   (match_operand:SWI48 3 "const_int_operand" "n")))
+                   (match_operand:SWI48 3 "const_int_operand")))
    (set (match_operand:SWI48 1 "register_operand" "=r")
        (umod:SWI48 (match_dup 2) (match_dup 3)))
    (clobber (reg:CC FLAGS_REG))]
@@ -9178,7 +9178,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI
          (udiv:SI (match_operand:SI 2 "register_operand" "0")
-                  (match_operand:SI 3 "const_int_operand" "n"))))
+                  (match_operand:SI 3 "const_int_operand"))))
    (set (match_operand:SI 1 "register_operand" "=r")
        (umod:SI (match_dup 2) (match_dup 3)))
    (clobber (reg:CC FLAGS_REG))]
@@ -9262,7 +9262,7 @@
   [(set (match_operand:DI 1 "register_operand" "=r")
        (zero_extend:DI
          (umod:SI (match_operand:SI 2 "register_operand" "0")
-                  (match_operand:SI 3 "const_int_operand" "n"))))
+                  (match_operand:SI 3 "const_int_operand"))))
    (set (match_operand:SI 0 "register_operand" "=r")
        (udiv:SI (match_dup 2) (match_dup 3)))
    (clobber (reg:CC FLAGS_REG))]
@@ -9329,7 +9329,7 @@
 ;; Avoid sign-extension (using cdq) for constant numerators.
 (define_insn_and_split "*divmodsi4_const"
   [(set (match_operand:SI 0 "register_operand" "=&a")
-       (div:SI (match_operand:SI 2 "const_int_operand" "n")
+       (div:SI (match_operand:SI 2 "const_int_operand")
                (match_operand:SI 3 "nonimmediate_operand" "rm")))
    (set (match_operand:SI 1 "register_operand" "=&d")
        (mod:SI (match_dup 2) (match_dup 3)))
@@ -9614,8 +9614,8 @@
         (match_operator 1 "compare_operator"
          [(zero_extract:SWI248
             (match_operand 2 "int_nonimmediate_operand" "rm")
-            (match_operand 3 "const_int_operand" "n")
-            (match_operand 4 "const_int_operand" "n"))
+            (match_operand 3 "const_int_operand")
+            (match_operand 4 "const_int_operand"))
           (const_int 0)]))]
   "/* Ensure that resulting mask is zero or sign extended operand.  */
    INTVAL (operands[4]) >= 0
@@ -11972,12 +11972,12 @@
 (define_insn "*x86_64_shld_1"
   [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
         (ior:DI (ashift:DI (match_dup 0)
-                          (match_operand:QI 2 "const_0_to_63_operand" "J"))
+                          (match_operand:QI 2 "const_0_to_63_operand"))
                (subreg:DI
                  (lshiftrt:TI
                    (zero_extend:TI
                      (match_operand:DI 1 "register_operand" "r"))
-                   (match_operand:QI 3 "const_0_to_255_operand" "N")) 0)))
+                   (match_operand:QI 3 "const_0_to_255_operand")) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT
    && INTVAL (operands[3]) == 64 - INTVAL (operands[2])"
@@ -12036,12 +12036,12 @@
 (define_insn "*x86_shld_1"
   [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
         (ior:SI (ashift:SI (match_dup 0)
-                          (match_operand:QI 2 "const_0_to_31_operand" "I"))
+                          (match_operand:QI 2 "const_0_to_31_operand"))
                (subreg:SI
                  (lshiftrt:DI
                    (zero_extend:DI
                      (match_operand:SI 1 "register_operand" "r"))
-                   (match_operand:QI 3 "const_0_to_63_operand" "J")) 0)))
+                   (match_operand:QI 3 "const_0_to_63_operand")) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "INTVAL (operands[3]) == 32 - INTVAL (operands[2])"
   "shld{l}\t{%2, %1, %0|%0, %1, %2}"
@@ -12561,7 +12561,7 @@
   [(set (reg FLAGS_REG)
        (compare
          (ashift:SI (match_operand:SI 1 "register_operand" "0")
-                    (match_operand:QI 2 "const_1_to_31_operand" "I"))
+                    (match_operand:QI 2 "const_1_to_31_operand"))
          (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
@@ -12895,12 +12895,12 @@
 (define_insn "*x86_64_shrd_1"
   [(set (match_operand:DI 0 "nonimmediate_operand" "+r*m")
         (ior:DI (lshiftrt:DI (match_dup 0)
-                            (match_operand:QI 2 "const_0_to_63_operand" "J"))
+                            (match_operand:QI 2 "const_0_to_63_operand"))
                (subreg:DI
                  (ashift:TI
                    (zero_extend:TI
                      (match_operand:DI 1 "register_operand" "r"))
-                   (match_operand:QI 3 "const_0_to_255_operand" "N")) 0)))
+                   (match_operand:QI 3 "const_0_to_255_operand")) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT
    && INTVAL (operands[3]) == 64 - INTVAL (operands[2])"
@@ -12959,12 +12959,12 @@
 (define_insn "*x86_shrd_1"
   [(set (match_operand:SI 0 "nonimmediate_operand" "+r*m")
         (ior:SI (lshiftrt:SI (match_dup 0)
-                            (match_operand:QI 2 "const_0_to_31_operand" "I"))
+                            (match_operand:QI 2 "const_0_to_31_operand"))
                (subreg:SI
                  (ashift:DI
                    (zero_extend:DI
                      (match_operand:SI 1 "register_operand" "r"))
-                   (match_operand:QI 3 "const_0_to_63_operand" "J")) 0)))
+                   (match_operand:QI 3 "const_0_to_63_operand")) 0)))
    (clobber (reg:CC FLAGS_REG))]
   "INTVAL (operands[3]) == 32 - INTVAL (operands[2])"
   "shrd{l}\t{%2, %1, %0|%0, %1, %2}"
@@ -13372,7 +13372,7 @@
   [(set (reg FLAGS_REG)
        (compare
          (any_shiftrt:SI (match_operand:SI 1 "register_operand" "0")
-                         (match_operand:QI 2 "const_1_to_31_operand" "I"))
+                         (match_operand:QI 2 "const_1_to_31_operand"))
          (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI (any_shiftrt:SI (match_dup 1) (match_dup 2))))]
@@ -13749,7 +13749,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
        (zero_extend:DI
          (rotatert:SI (match_operand:SI 1 "nonimmediate_operand" "rm")
-                      (match_operand:QI 2 "const_0_to_31_operand" "I"))))]
+                      (match_operand:QI 2 "const_0_to_31_operand"))))]
   "TARGET_64BIT && TARGET_BMI2 && !optimize_function_for_size_p (cfun)"
   "rorx\t{%2, %1, %k0|%k0, %1, %2}"
   [(set_attr "type" "rotatex")
@@ -14102,7 +14102,7 @@
 (define_insn "*btsq_imm"
   [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm")
                         (const_int 1)
-                        (match_operand 1 "const_0_to_63_operand" "J"))
+                        (match_operand 1 "const_0_to_63_operand"))
        (const_int 1))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
@@ -14115,7 +14115,7 @@
 (define_insn "*btrq_imm"
   [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm")
                         (const_int 1)
-                        (match_operand 1 "const_0_to_63_operand" "J"))
+                        (match_operand 1 "const_0_to_63_operand"))
        (const_int 0))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
@@ -14128,7 +14128,7 @@
 (define_insn "*btcq_imm"
   [(set (zero_extract:DI (match_operand:DI 0 "nonimmediate_operand" "+rm")
                         (const_int 1)
-                        (match_operand 1 "const_0_to_63_operand" "J"))
+                        (match_operand 1 "const_0_to_63_operand"))
        (not:DI (zero_extract:DI (match_dup 0) (const_int 1) (match_dup 1))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && (TARGET_USE_BT || reload_completed)"
@@ -14656,7 +14656,7 @@
        (unspec:QI
          [(match_operand:HF 1 "register_operand" "v")
           (match_operand:HF 2 "nonimmediate_operand" "vm")
-          (match_operand:SI 3 "const_0_to_31_operand" "n")]
+          (match_operand:SI 3 "const_0_to_31_operand")]
          UNSPEC_PCMP))]
   "TARGET_AVX512FP16"
   "vcmpsh\t{%3, %2, %1, %0|%0, %1, %2, %3}"
@@ -16673,7 +16673,7 @@
          (zero_extract:SWI48
            (match_operand:SWI48 1 "nonimmediate_operand" "rm")
            (umin:SWI48 (and:SWI48 (match_dup 2) (const_int 255))
-                       (match_operand:SWI48 3 "const_int_operand" "n"))
+                       (match_operand:SWI48 3 "const_int_operand"))
            (const_int 0))
          (const_int 0)))
    (clobber (reg:CC FLAGS_REG))]
@@ -16690,7 +16690,7 @@
          (zero_extract:SWI48
            (match_operand:SWI48 1 "nonimmediate_operand" "rm")
            (umin:SWI48 (zero_extend:SWI48 (match_dup 2))
-                       (match_operand:SWI48 3 "const_int_operand" "n"))
+                       (match_operand:SWI48 3 "const_int_operand"))
            (const_int 0))
          (const_int 0)))
    (clobber (reg:CC FLAGS_REG))]
@@ -16708,7 +16708,7 @@
            (zero_extract:SWI48
              (match_operand:SWI48 1 "nonimmediate_operand" "rm")
              (umin:SWI48 (zero_extend:SWI48 (match_dup 2))
-                         (match_operand:SWI48 3 "const_int_operand" "n"))
+                         (match_operand:SWI48 3 "const_int_operand"))
              (const_int 0))
            (const_int 0))
        (const_int 0)))
@@ -16791,8 +16791,8 @@
   [(set (match_operand:SWI48 0 "register_operand" "=r")
         (zero_extract:SWI48
           (match_operand:SWI48 1 "nonimmediate_operand" "rm")
-          (match_operand 2 "const_0_to_255_operand" "N")
-          (match_operand 3 "const_0_to_255_operand" "N")))
+          (match_operand 2 "const_0_to_255_operand")
+          (match_operand 3 "const_0_to_255_operand")))
    (clobber (reg:CC FLAGS_REG))]
    "TARGET_TBM"
 {
@@ -19415,7 +19415,7 @@
   [(set (match_operand:MODEFH 0 "register_operand" "=x,x,x,v,v")
        (unspec:MODEFH
          [(match_operand:MODEFH 1 "nonimmediate_operand" "0,x,m,v,m")
-          (match_operand:SI 2 "const_0_to_15_operand" "n,n,n,n,n")]
+          (match_operand:SI 2 "const_0_to_15_operand")]
          UNSPEC_ROUND))]
   "TARGET_SSE4_1"
   "@
@@ -21607,7 +21607,7 @@
        (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")]
                            UNSPECV_PROBE_STACK_RANGE))
    (set (reg:P SP_REG)
-        (minus:P (reg:P SP_REG) (match_operand:P 2 "const_int_operand" "n")))
+        (minus:P (reg:P SP_REG) (match_operand:P 2 "const_int_operand")))
    (clobber (reg:CC FLAGS_REG))
    (clobber (mem:BLK (scratch)))]
   ""
@@ -21617,7 +21617,7 @@
 (define_insn "@probe_stack_range_<mode>"
   [(set (match_operand:P 0 "register_operand" "=r")
        (unspec_volatile:P [(match_operand:P 1 "register_operand" "0")
-                           (match_operand:P 2 "const_int_operand" "n")]
+                           (match_operand:P 2 "const_int_operand")]
                            UNSPECV_PROBE_STACK_RANGE))
    (clobber (reg:CC FLAGS_REG))]
   ""
@@ -23061,7 +23061,7 @@
 
 (define_insn "*prefetch_3dnow"
   [(prefetch (match_operand 0 "address_operand" "p")
-            (match_operand:SI 1 "const_int_operand" "n")
+            (match_operand:SI 1 "const_int_operand")
             (const_int 3))]
   "TARGET_3DNOW || TARGET_PRFCHW || TARGET_PREFETCHWT1"
 {
@@ -23611,7 +23611,7 @@
 (define_insn "@lwp_lwpval<mode>"
   [(unspec_volatile [(match_operand:SWI48 0 "register_operand" "r")
                     (match_operand:SI 1 "nonimmediate_operand" "rm")
-                    (match_operand:SI 2 "const_int_operand" "i")]
+                    (match_operand:SI 2 "const_int_operand")]
                    UNSPECV_LWPVAL_INTRINSIC)]
   "TARGET_LWP"
   "lwpval\t{%2, %1, %0|%0, %1, %2}"
@@ -23624,7 +23624,7 @@
   [(set (reg:CCC FLAGS_REG)
        (unspec_volatile:CCC [(match_operand:SWI48 0 "register_operand" "r")
                              (match_operand:SI 1 "nonimmediate_operand" "rm")
-                             (match_operand:SI 2 "const_int_operand" "i")]
+                             (match_operand:SI 2 "const_int_operand")]
                             UNSPECV_LWPINS_INTRINSIC))]
   "TARGET_LWP"
   "lwpins\t{%2, %1, %0|%0, %1, %2}"
@@ -23830,7 +23830,7 @@
    (set_attr "length" "3")])
 
 (define_insn "xabort"
-  [(unspec_volatile [(match_operand:SI 0 "const_0_to_255_operand" "n")]
+  [(unspec_volatile [(match_operand:SI 0 "const_0_to_255_operand")]
                    UNSPECV_XABORT)]
   "TARGET_RTM"
   "xabort\t%0"

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 197f19e..03aa01f 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -3454,7 +3454,7 @@
   [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,m")
        (vec_select:HI
          (match_operand:V4HI 1 "register_operand" "y,YW,YW")
-         (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n")])))]
+         (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
   "(TARGET_MMX || TARGET_MMX_WITH_SSE)
    && (TARGET_SSE || TARGET_3DNOW_A)"
   "@
@@ -3473,7 +3473,7 @@
        (zero_extend:SWI48
          (vec_select:HI
            (match_operand:V4HI 1 "register_operand" "y,YW")
-           (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))]
+           (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))]
   "(TARGET_MMX || TARGET_MMX_WITH_SSE)
    && (TARGET_SSE || TARGET_3DNOW_A)"
   "@
@@ -3490,7 +3490,7 @@
   [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m")
        (vec_select:QI
          (match_operand:V8QI 1 "register_operand" "YW,YW")
-         (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n,n")])))]
+         (parallel [(match_operand:SI 2 "const_0_to_7_operand")])))]
   "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
   "@
    %vpextrb\t{%2, %1, %k0|%k0, %1, %2}
@@ -3507,7 +3507,7 @@
        (zero_extend:SWI248
          (vec_select:QI
            (match_operand:V8QI 1 "register_operand" "YW")
-           (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))]
+           (parallel [(match_operand:SI 2 "const_0_to_7_operand")]))))]
   "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
   "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
   [(set_attr "type" "sselog1")
@@ -3630,7 +3630,7 @@
        (vec_merge:V4HI
          (match_operand:V4HI 2 "register_operand" "Yr,*x,x")
          (match_operand:V4HI 1 "register_operand" "0,0,x")
-         (match_operand:SI 3 "const_0_to_15_operand" "n,n,n")))]
+         (match_operand:SI 3 "const_0_to_15_operand")))]
   "TARGET_SSE4_1 && TARGET_MMX_WITH_SSE"
   "@
    pblendw\t{%3, %2, %0|%0, %2, %3}
@@ -3648,7 +3648,7 @@
        (vec_merge:V2HI
          (match_operand:V2HI 2 "register_operand" "Yr,*x,x")
          (match_operand:V2HI 1 "register_operand" "0,0,x")
-         (match_operand:SI 3 "const_0_to_7_operand" "n,n,n")))]
+         (match_operand:SI 3 "const_0_to_7_operand")))]
   "TARGET_SSE4_1"
   "@
    pblendw\t{%3, %2, %0|%0, %2, %3}
@@ -4035,7 +4035,7 @@
   [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,m")
        (vec_select:HI
          (match_operand:V2HI 1 "register_operand" "YW,YW")
-         (parallel [(match_operand:SI 2 "const_0_to_1_operand" "n,n")])))]
+         (parallel [(match_operand:SI 2 "const_0_to_1_operand")])))]
   "TARGET_SSE2"
   "@
    %vpextrw\t{%2, %1, %k0|%k0, %1, %2}
@@ -4051,7 +4051,7 @@
        (zero_extend:SWI48
          (vec_select:HI
            (match_operand:V2HI 1 "register_operand" "YW")
-           (parallel [(match_operand:SI 2 "const_0_to_1_operand" "n")]))))]
+           (parallel [(match_operand:SI 2 "const_0_to_1_operand")]))))]
   "TARGET_SSE2"
   "%vpextrw\t{%2, %1, %k0|%k0, %1, %2}"
   [(set_attr "type" "sselog1")
@@ -4063,7 +4063,7 @@
   [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m")
        (vec_select:QI
          (match_operand:V4QI 1 "register_operand" "YW,YW")
-         (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")])))]
+         (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
   "TARGET_SSE4_1"
   "@
    %vpextrb\t{%2, %1, %k0|%k0, %1, %2}
@@ -4080,7 +4080,7 @@
        (zero_extend:SWI248
          (vec_select:QI
            (match_operand:V4QI 1 "register_operand" "YW")
-           (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")]))))]
+           (parallel [(match_operand:SI 2 "const_0_to_3_operand")]))))]
   "TARGET_SSE4_1"
   "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}"
   [(set_attr "type" "sselog1")

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 8b2602b..5eb48c3 100644 (file)
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -1484,7 +1484,7 @@
              (match_operand:MODEFH 1 "memory_operand" "m"))
            (match_operand:<ssevecmode> 2 "nonimm_or_0_operand" "0C")
            (match_operand:QI 3 "register_operand" "Yk"))
-         (match_operand:<ssevecmode> 4 "const0_operand" "C")
+         (match_operand:<ssevecmode> 4 "const0_operand")
          (const_int 1)))]
   "TARGET_AVX512F"
   "vmov<ssescalarmodesuffix>\t{%1, %0%{%3%}%N2|%0%{3%}%N2, %1}"
@@ -1624,7 +1624,7 @@
          (vec_select:<ssescalarmode>
            (match_operand:VI8F_128 1 "nonimmediate_operand" "vm")
            (parallel [(const_int 0)]))
-         (match_operand:<ssescalarmode> 2 "const0_operand" "C")))]
+         (match_operand:<ssescalarmode> 2 "const0_operand")))]
   "TARGET_SSE2"
   "%vmovq\t{%1, %0|%0, %q1}"
   [(set_attr "type" "ssemov")
@@ -2018,7 +2018,7 @@
   [(set (match_operand:SWI1248_AVX512BWDQ 0 "register_operand" "=k")
        (any_lshift:SWI1248_AVX512BWDQ
          (match_operand:SWI1248_AVX512BWDQ 1 "register_operand" "k")
-         (match_operand 2 "const_0_to_255_operand" "n")))
+         (match_operand 2 "const_0_to_255_operand")))
    (unspec [(const_int 0)] UNSPEC_MASKOP)]
   "TARGET_AVX512F"
   "k<mshift><mskmodesuffix>\t{%2, %1, %0|%0, %1, %2}"
@@ -3440,7 +3440,7 @@
        (unspec:VF_128_256
          [(match_operand:VF_128_256 1 "register_operand" "x")
           (match_operand:VF_128_256 2 "nonimmediate_operand" "xm")
-          (match_operand:SI 3 "const_0_to_31_operand" "n")]
+          (match_operand:SI 3 "const_0_to_31_operand")]
          UNSPEC_PCMP))]
   "TARGET_AVX"
   "vcmp<ssemodesuffix>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
@@ -3652,7 +3652,7 @@
          (unspec:VF_128
            [(match_operand:VF_128 1 "register_operand" "x")
             (match_operand:VF_128 2 "nonimmediate_operand" "xm")
-            (match_operand:SI 3 "const_0_to_31_operand" "n")]
+            (match_operand:SI 3 "const_0_to_31_operand")]
            UNSPEC_PCMP)
         (match_dup 1)
         (const_int 1)))]
@@ -3745,7 +3745,7 @@
          (unspec:<V48H_AVX512VL:avx512fmaskmode>
            [(match_operand:V48H_AVX512VL 1 "nonimmediate_operand")
             (match_operand:V48H_AVX512VL 2 "nonimmediate_operand")
-            (match_operand:SI 3 "const_0_to_7_operand" "n")]
+            (match_operand:SI 3 "const_0_to_7_operand")]
            UNSPEC_PCMP)))]
   "TARGET_AVX512F
    && (!VALID_MASK_AVX512BW_MODE (<SWI248x:MODE>mode) || TARGET_AVX512BW)
@@ -3951,7 +3951,7 @@
        (unspec:<avx512fmaskmode>
          [(match_operand:VI12_AVX512VL 1 "register_operand" "v")
           (match_operand:VI12_AVX512VL 2 "nonimmediate_operand" "vm")
-          (match_operand:SI 3 "const_0_to_7_operand" "n")]
+          (match_operand:SI 3 "const_0_to_7_operand")]
          UNSPEC_UNSIGNED_PCMP))]
   "TARGET_AVX512BW"
   "vpcmpu<ssemodesuffix>\t{%3, %2, %1, %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2, %3}"
@@ -4049,7 +4049,7 @@
        (unspec:<avx512fmaskmode>
          [(match_operand:VI48_AVX512VL 1 "register_operand" "v")
           (match_operand:VI48_AVX512VL 2 "nonimmediate_operand" "vm")
-          (match_operand:SI 3 "const_0_to_7_operand" "n")]
+          (match_operand:SI 3 "const_0_to_7_operand")]
          UNSPEC_UNSIGNED_PCMP))]
   "TARGET_AVX512F"
   "vpcmpu<ssemodesuffix>\t{%3, %2, %1, %0<mask_scalar_merge_operand4>|%0<mask_scalar_merge_operand4>, %1, %2, %3}"
@@ -4189,7 +4189,7 @@
          (unspec:<avx512fmaskmode>
            [(match_operand:VFH_128 1 "register_operand" "v")
             (match_operand:VFH_128 2 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
-            (match_operand:SI 3 "const_0_to_31_operand" "n")]
+            (match_operand:SI 3 "const_0_to_31_operand")]
            UNSPEC_PCMP)
          (const_int 1)))]
   "TARGET_AVX512F"
@@ -4205,7 +4205,7 @@
          (unspec:<avx512fmaskmode>
            [(match_operand:VFH_128 1 "register_operand" "v")
             (match_operand:VFH_128 2 "<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
-            (match_operand:SI 3 "const_0_to_31_operand" "n")]
+            (match_operand:SI 3 "const_0_to_31_operand")]
            UNSPEC_PCMP)
          (and:<avx512fmaskmode>
            (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk")
@@ -6081,7 +6081,7 @@
              (match_operand:VFH_128 1 "register_operand" "0,0")
              (match_operand:VFH_128 2 "<round_nimm_scalar_predicate>" "<round_constraint>,v")
              (match_operand:VFH_128 3 "<round_nimm_scalar_predicate>" "v,<round_constraint>"))
-           (match_operand:VFH_128 4 "const0_operand" "C,C")
+           (match_operand:VFH_128 4 "const0_operand")
            (match_operand:QI 5 "register_operand" "Yk,Yk"))
          (match_dup 1)
          (const_int 1)))]
@@ -6139,7 +6139,7 @@
              (match_operand:VFH_128 2 "<round_nimm_scalar_predicate>" "<round_constraint>,v")
              (neg:VFH_128
                (match_operand:VFH_128 3 "<round_nimm_scalar_predicate>" "v,<round_constraint>")))
-           (match_operand:VFH_128 4 "const0_operand" "C,C")
+           (match_operand:VFH_128 4 "const0_operand")
            (match_operand:QI 5 "register_operand" "Yk,Yk"))
          (match_dup 1)
          (const_int 1)))]
@@ -6211,7 +6211,7 @@
                (match_operand:VFH_128 2 "<round_nimm_scalar_predicate>" "<round_constraint>,v"))
              (match_operand:VFH_128 1 "register_operand" "0,0")
              (match_operand:VFH_128 3 "<round_nimm_scalar_predicate>" "v,<round_constraint>"))
-           (match_operand:VFH_128 4 "const0_operand" "C,C")
+           (match_operand:VFH_128 4 "const0_operand")
            (match_operand:QI 5 "register_operand" "Yk,Yk"))
          (match_dup 1)
          (const_int 1)))]
@@ -6272,7 +6272,7 @@
              (match_operand:VFH_128 1 "register_operand" "0,0")
              (neg:VFH_128
                (match_operand:VFH_128 3 "<round_nimm_scalar_predicate>" "v,<round_constraint>")))
-           (match_operand:VFH_128 4 "const0_operand" "C,C")
+           (match_operand:VFH_128 4 "const0_operand")
            (match_operand:QI 5 "register_operand" "Yk,Yk"))
          (match_dup 1)
          (const_int 1)))]
@@ -6937,7 +6937,7 @@
   [(set (match_operand:V8HF 0 "register_operand" "=v")
        (vec_concat:V8HF
            (any_float:V4HF (match_operand:VI4_128_8_256 1 "vector_operand" "vm"))
-           (match_operand:V4HF 2 "const0_operand" "C")))]
+           (match_operand:V4HF 2 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvt<floatsuffix><sseintconvert>2ph<qq2phsuff>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
@@ -6966,7 +6966,7 @@
                 (match_operand:V8HF 2 "nonimm_or_0_operand" "0C")
                 (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))
             (match_operand:QI 3 "register_operand" "Yk"))
-           (match_operand:V4HF 4 "const0_operand" "C")))]
+           (match_operand:V4HF 4 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvt<floatsuffix><sseintconvert>2ph<qq2phsuff>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
   [(set_attr "type" "ssecvt")
@@ -6979,9 +6979,9 @@
        (vec_merge:V4HF
                (any_float:V4HF (match_operand:VI4_128_8_256 1
                                  "vector_operand" "vm"))
-           (match_operand:V4HF 3 "const0_operand" "C")
+           (match_operand:V4HF 3 "const0_operand")
            (match_operand:QI 2 "register_operand" "Yk"))
-           (match_operand:V4HF 4 "const0_operand" "C")))]
+           (match_operand:V4HF 4 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvt<floatsuffix><sseintconvert>2ph<qq2phsuff>\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
   [(set_attr "type" "ssecvt")
@@ -7013,7 +7013,7 @@
   [(set (match_operand:V8HF 0 "register_operand" "=v")
        (vec_concat:V8HF
            (any_float:V2HF (match_operand:V2DI 1 "vector_operand" "vm"))
-           (match_operand:V6HF 2 "const0_operand" "C")))]
+           (match_operand:V6HF 2 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvt<floatsuffix>qq2ph{x}\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
@@ -7042,7 +7042,7 @@
                 (match_operand:V8HF 2 "nonimm_or_0_operand" "0C")
                 (parallel [(const_int 0) (const_int 1)]))
             (match_operand:QI 3 "register_operand" "Yk"))
-           (match_operand:V6HF 4 "const0_operand" "C")))]
+           (match_operand:V6HF 4 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvt<floatsuffix>qq2ph{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
   [(set_attr "type" "ssecvt")
@@ -7055,9 +7055,9 @@
        (vec_merge:V2HF
                (any_float:V2HF (match_operand:V2DI 1
                                  "vector_operand" "vm"))
-           (match_operand:V2HF 3 "const0_operand" "C")
+           (match_operand:V2HF 3 "const0_operand")
            (match_operand:QI 2 "register_operand" "Yk"))
-           (match_operand:V6HF 4 "const0_operand" "C")))]
+           (match_operand:V6HF 4 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvt<floatsuffix>qq2ph{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
   [(set_attr "type" "ssecvt")
@@ -7360,7 +7360,7 @@
        (vec_concat:V8HF
            (float_truncate:V4HF
              (match_operand:VF4_128_8_256 1 "vector_operand" "vm"))
-           (match_operand:V4HF 2 "const0_operand" "C")))]
+           (match_operand:V4HF 2 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvt<castmode>2ph<ph2pssuffix><qq2phsuff>\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
@@ -7393,7 +7393,7 @@
              (parallel [(const_int 0) (const_int 1)
                         (const_int 2) (const_int 3)]))
            (match_operand:QI 3 "register_operand" "Yk"))
-         (match_operand:V4HF 4 "const0_operand" "C")))]
+         (match_operand:V4HF 4 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvt<castmode>2ph<ph2pssuffix><qq2phsuff>\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
   [(set_attr "type" "ssecvt")
@@ -7406,9 +7406,9 @@
          (vec_merge:V4HF
            (float_truncate:V4HF
              (match_operand:VF4_128_8_256 1 "vector_operand" "vm"))
-           (match_operand:V4HF 3 "const0_operand" "C")
+           (match_operand:V4HF 3 "const0_operand")
            (match_operand:QI 2 "register_operand" "Yk"))
-         (match_operand:V4HF 4 "const0_operand" "C")))]
+         (match_operand:V4HF 4 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvt<castmode>2ph<ph2pssuffix><qq2phsuff>\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
   [(set_attr "type" "ssecvt")
@@ -7439,7 +7439,7 @@
        (vec_concat:V8HF
          (float_truncate:V2HF
            (match_operand:V2DF 1 "vector_operand" "vm"))
-         (match_operand:V6HF 2 "const0_operand" "C")))]
+         (match_operand:V6HF 2 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvtpd2ph{x}\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
@@ -7469,7 +7469,7 @@
              (match_operand:V8HF 2 "nonimm_or_0_operand" "0C")
              (parallel [(const_int 0) (const_int 1)]))
            (match_operand:QI 3 "register_operand" "Yk"))
-         (match_operand:V6HF 4 "const0_operand" "C")))]
+         (match_operand:V6HF 4 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvtpd2ph{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
   [(set_attr "type" "ssecvt")
@@ -7482,9 +7482,9 @@
          (vec_merge:V2HF
            (float_truncate:V2HF
              (match_operand:V2DF 1 "vector_operand" "vm"))
-           (match_operand:V2HF 3 "const0_operand" "C")
+           (match_operand:V2HF 3 "const0_operand")
            (match_operand:QI 2 "register_operand" "Yk"))
-         (match_operand:V6HF 4 "const0_operand" "C")))]
+         (match_operand:V6HF 4 "const0_operand")))]
   "TARGET_AVX512FP16 && TARGET_AVX512VL"
   "vcvtpd2ph{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
   [(set_attr "type" "ssecvt")
@@ -8268,7 +8268,7 @@
   [(set (match_operand:V4SF 0 "register_operand" "=v")
        (vec_concat:V4SF
            (any_float:V2SF (match_operand:V2DI 1 "nonimmediate_operand" "vm"))
-           (match_operand:V2SF 2 "const0_operand" "C")))]
+           (match_operand:V2SF 2 "const0_operand")))]
   "TARGET_AVX512DQ && TARGET_AVX512VL"
   "vcvt<floatsuffix>qq2ps{x}\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssecvt")
@@ -8343,7 +8343,7 @@
                 (match_operand:V4SF 2 "nonimm_or_0_operand" "0C")
                 (parallel [(const_int 0) (const_int 1)]))
             (match_operand:QI 3 "register_operand" "Yk"))
-           (match_operand:V2SF 4 "const0_operand" "C")))]
+           (match_operand:V2SF 4 "const0_operand")))]
   "TARGET_AVX512DQ && TARGET_AVX512VL"
   "vcvt<floatsuffix>qq2ps{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
   [(set_attr "type" "ssecvt")
@@ -8356,9 +8356,9 @@
        (vec_merge:V2SF
                (any_float:V2SF (match_operand:V2DI 1
                                  "nonimmediate_operand" "vm"))
-           (match_operand:V2SF 3 "const0_operand" "C")
+           (match_operand:V2SF 3 "const0_operand")
            (match_operand:QI 2 "register_operand" "Yk"))
-           (match_operand:V2SF 4 "const0_operand" "C")))]
+           (match_operand:V2SF 4 "const0_operand")))]
   "TARGET_AVX512DQ && TARGET_AVX512VL"
   "vcvt<floatsuffix>qq2ps{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
   [(set_attr "type" "ssecvt")
@@ -8982,7 +8982,7 @@
        (vec_concat:V4SF
          (float_truncate:V2SF
            (match_operand:V2DF 1 "vector_operand" "vBm"))
-         (match_operand:V2SF 2 "const0_operand" "C")))]
+         (match_operand:V2SF 2 "const0_operand")))]
   "TARGET_SSE2"
 {
   if (TARGET_AVX)
@@ -9027,7 +9027,7 @@
              (match_operand:V4SF 2 "nonimm_or_0_operand" "0C")
              (parallel [(const_int 0) (const_int 1)]))
            (match_operand:QI 3 "register_operand" "Yk"))
-         (match_operand:V2SF 4 "const0_operand" "C")))]
+         (match_operand:V2SF 4 "const0_operand")))]
   "TARGET_AVX512VL"
   "vcvtpd2ps{x}\t{%1, %0%{%3%}%N2|%0%{%3%}%N2, %1}"
   [(set_attr "type" "ssecvt")
@@ -9040,9 +9040,9 @@
          (vec_merge:V2SF
            (float_truncate:V2SF
              (match_operand:V2DF 1 "nonimmediate_operand" "vm"))
-           (match_operand:V2SF 3 "const0_operand" "C")
+           (match_operand:V2SF 3 "const0_operand")
            (match_operand:QI 2 "register_operand" "Yk"))
-         (match_operand:V2SF 4 "const0_operand" "C")))]
+         (match_operand:V2SF 4 "const0_operand")))]
   "TARGET_AVX512VL"
   "vcvtpd2ps{x}\t{%1, %0%{%2%}%{z%}|%0%{%2%}%{z%}, %1}"
   [(set_attr "type" "ssecvt")
@@ -10577,7 +10577,7 @@
   [(set (match_operand:V4SF 0 "register_operand"       "=v")
        (vec_concat:V4SF
          (match_operand:V2SF 1 "nonimmediate_operand" "vm")
-         (match_operand:V2SF 2 "const0_operand"       " C")))]
+         (match_operand:V2SF 2 "const0_operand")))]
   "TARGET_SSE2"
   "%vmovq\t{%1, %0|%0, %1}"
   [(set_attr "type" "ssemov")
@@ -10735,7 +10735,7 @@
        (vec_merge:VI2F_256_512
          (vec_duplicate:VI2F_256_512
            (match_operand:<ssescalarmode> 2 "nonimmediate_operand" "r,m"))
-         (match_operand:VI2F_256_512 1 "const0_operand" "C,C")
+         (match_operand:VI2F_256_512 1 "const0_operand")
          (const_int 1)))]
   "TARGET_AVX512FP16"
   "@
@@ -10835,7 +10835,7 @@
        (vec_merge:VI4F_256_512
          (vec_duplicate:VI4F_256_512
            (match_operand:<ssescalarmode> 2 "nonimmediate_operand" "v,m,r"))
-         (match_operand:VI4F_256_512 1 "const0_operand" "C,C,C")
+         (match_operand:VI4F_256_512 1 "const0_operand")
          (const_int 1)))]
   "TARGET_AVX"
   "@
@@ -10898,7 +10898,7 @@
   [(set (match_operand:V4SF 0 "register_operand" "=Yr,*x,v")
        (unspec:V4SF [(match_operand:V4SF 2 "nonimmediate_operand" "Yrm,*xm,vm")
                      (match_operand:V4SF 1 "register_operand" "0,0,v")
-                     (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")]
+                     (match_operand:SI 3 "const_0_to_255_operand")]
                     UNSPEC_INSERTPS))]
   "TARGET_SSE4_1"
 {
@@ -11015,7 +11015,7 @@
   [(set (match_operand:SF 0 "nonimmediate_operand" "=rm,rm,rm,Yv,Yv")
        (vec_select:SF
          (match_operand:V4SF 1 "register_operand" "Yr,*x,v,0,v")
-         (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n,n,n")])))]
+         (parallel [(match_operand:SI 2 "const_0_to_3_operand")])))]
   "TARGET_SSE4_1"
   "@
    extractps\t{%2, %1, %0|%0, %1, %2}
@@ -11057,7 +11057,7 @@
   [(set (match_operand:SF 0 "register_operand" "=v,*r,f")
        (vec_select:SF
          (match_operand:V4SF 1 "memory_operand" "o,o,o")
-         (parallel [(match_operand 2 "const_0_to_3_operand" "n,n,n")])))]
+         (parallel [(match_operand 2 "const_0_to_3_operand")])))]
   "TARGET_SSE"
   "#"
   "&& reload_completed"
@@ -13540,7 +13540,7 @@
        (vec_merge:VF2_512_256
          (vec_duplicate:VF2_512_256
            (match_operand:<ssescalarmode> 2 "nonimmediate_operand" "vm"))
-         (match_operand:VF2_512_256 1 "const0_operand" "C")
+         (match_operand:VF2_512_256 1 "const0_operand")
          (const_int 1)))]
   "TARGET_AVX"
   "vmovq\t{%2, %x0|%x0, %2}"
@@ -16028,7 +16028,7 @@
   [(set (match_operand:VIMAX_AVX512VL 0 "register_operand" "=v")
        (any_lshift:VIMAX_AVX512VL
         (match_operand:VIMAX_AVX512VL 1 "nonimmediate_operand" "vm")
-        (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n")))]
+        (match_operand:SI 2 "const_0_to_255_mul_8_operand")))]
   "TARGET_AVX512BW"
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
@@ -16043,7 +16043,7 @@
   [(set (match_operand:VIMAX_AVX2 0 "register_operand" "=x,Yw")
        (any_lshift:VIMAX_AVX2
         (match_operand:VIMAX_AVX2 1 "register_operand" "0,Yw")
-        (match_operand:SI 2 "const_0_to_255_mul_8_operand" "n,n")))]
+        (match_operand:SI 2 "const_0_to_255_mul_8_operand")))]
   "TARGET_SSE2"
 {
   operands[2] = GEN_INT (INTVAL (operands[2]) / 8);
@@ -18102,7 +18102,7 @@
          (match_operand:AVX512_VEC 1 "reg_or_0_operand" "v,C,C")
          (vec_duplicate:AVX512_VEC
                (match_operand:<ssequartermode> 2 "nonimmediate_operand" "vm,xm,vm"))
-         (match_operand:SI 3 "const_int_operand" "n,n,n")))]
+         (match_operand:SI 3 "const_int_operand")))]
   "TARGET_AVX512F
    && (INTVAL (operands[3])
        == (GET_MODE_UNIT_SIZE (<MODE>mode) == 4 ? 0xFFF0 : 0xFC))"
@@ -18150,7 +18150,7 @@
          (match_operand:AVX512_VEC 1 "register_operand" "v")
          (vec_duplicate:AVX512_VEC
                (match_operand:<ssequartermode> 2 "nonimmediate_operand" "vm"))
-         (match_operand:SI 3 "const_int_operand" "n")))]
+         (match_operand:SI 3 "const_int_operand")))]
   "TARGET_AVX512F"
 {
   int mask;
@@ -18818,7 +18818,7 @@
   [(set (match_operand:V32HI 0 "register_operand" "=v")
        (unspec:V32HI
          [(match_operand:V32HI 1 "nonimmediate_operand" "vm")
-          (match_operand:SI 2 "const_0_to_255_operand" "n")]
+          (match_operand:SI 2 "const_0_to_255_operand")]
          UNSPEC_PSHUFLW))]
   "TARGET_AVX512BW"
   "vpshuflw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -18994,7 +18994,7 @@
   [(set (match_operand:V32HI 0 "register_operand" "=v")
        (unspec:V32HI
          [(match_operand:V32HI 1 "nonimmediate_operand" "vm")
-          (match_operand:SI 2 "const_0_to_255_operand" "n")]
+          (match_operand:SI 2 "const_0_to_255_operand")]
          UNSPEC_PSHUFHW))]
   "TARGET_AVX512BW"
   "vpshufhw\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -19726,7 +19726,7 @@
   [(set (match_operand:VI124_128 0 "register_operand"       "=v,x")
        (vec_concat:VI124_128
          (match_operand:<ssehalfvecmode> 1 "nonimmediate_operand" "vm,?!*y")
-         (match_operand:<ssehalfvecmode> 2 "const0_operand"       " C,C")))]
+         (match_operand:<ssehalfvecmode> 2 "const0_operand")))]
   "TARGET_SSE2"
   "@
    %vmovq\t{%1, %0|%0, %1}
@@ -19800,7 +19800,7 @@
   [(set (match_operand:V2DI 0 "register_operand"     "=v,v ,x")
        (vec_concat:V2DI
          (match_operand:DI 1 "nonimmediate_operand" " r,vm,?!*y")
-         (match_operand:DI 2 "const0_operand"       " C,C ,C")))]
+         (match_operand:DI 2 "const0_operand")))]
   "TARGET_SSE2"
   "@
    * return HAVE_AS_IX86_INTERUNIT_MOVQ ? \"%vmovq\t{%1, %0|%0, %1}\" : \"%vmovd\t{%1, %0|%0, %1}\";
@@ -19824,7 +19824,7 @@
        (vec_merge:VI8_AVX_AVX512F
          (vec_duplicate:VI8_AVX_AVX512F
            (match_operand:<ssescalarmode> 2 "nonimmediate_operand" "r,vm"))
-         (match_operand:VI8_AVX_AVX512F 1 "const0_operand" "C,C")
+         (match_operand:VI8_AVX_AVX512F 1 "const0_operand")
          (const_int 1)))]
   "TARGET_AVX"
   "vmovq\t{%2, %x0|%x0, %2}"
@@ -20025,7 +20025,7 @@
        (unspec:SI
          [(lt:VF_128_256
             (match_operand:<sseintvecmode> 1 "register_operand" "x")
-            (match_operand:<sseintvecmode> 2 "const0_operand" "C"))]
+            (match_operand:<sseintvecmode> 2 "const0_operand"))]
          UNSPEC_MOVMSK))]
   "TARGET_SSE"
   "#"
@@ -20043,7 +20043,7 @@
          (unspec:SI
            [(lt:VF_128_256
               (match_operand:<sseintvecmode> 1 "register_operand" "x")
-              (match_operand:<sseintvecmode> 2 "const0_operand" "C"))]
+              (match_operand:<sseintvecmode> 2 "const0_operand"))]
            UNSPEC_MOVMSK)))]
   "TARGET_64BIT && TARGET_SSE"
   "#"
@@ -20061,7 +20061,7 @@
          [(subreg:VF_128_256
             (ashiftrt:<sseintvecmode>
               (match_operand:<sseintvecmode> 1 "register_operand" "x")
-              (match_operand:QI 2 "const_int_operand" "n")) 0)]
+              (match_operand:QI 2 "const_int_operand")) 0)]
          UNSPEC_MOVMSK))]
   "TARGET_SSE"
   "#"
@@ -20080,7 +20080,7 @@
            [(subreg:VF_128_256
               (ashiftrt:<sseintvecmode>
                 (match_operand:<sseintvecmode> 1 "register_operand" "x")
-              (match_operand:QI 2 "const_int_operand" "n")) 0)]
+              (match_operand:QI 2 "const_int_operand")) 0)]
            UNSPEC_MOVMSK)))]
   "TARGET_64BIT && TARGET_SSE"
   "#"
@@ -20221,7 +20221,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
        (unspec:SI
          [(lt:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand" "x")
-                       (match_operand:VI1_AVX2 2 "const0_operand" "C"))]
+                       (match_operand:VI1_AVX2 2 "const0_operand"))]
          UNSPEC_MOVMSK))]
   "TARGET_SSE2"
   "#"
@@ -20243,7 +20243,7 @@
        (zero_extend:DI
          (unspec:SI
            [(lt:VI1_AVX2 (match_operand:VI1_AVX2 1 "register_operand" "x")
-                         (match_operand:VI1_AVX2 2 "const0_operand" "C"))]
+                         (match_operand:VI1_AVX2 2 "const0_operand"))]
            UNSPEC_MOVMSK)))]
   "TARGET_64BIT && TARGET_SSE2"
   "#"
@@ -20265,7 +20265,7 @@
        (sign_extend:DI
          (unspec:SI
            [(lt:V16QI (match_operand:V16QI 1 "register_operand" "x")
-                      (match_operand:V16QI 2 "const0_operand" "C"))]
+                      (match_operand:V16QI 2 "const0_operand"))]
            UNSPEC_MOVMSK)))]
   "TARGET_64BIT && TARGET_SSE2"
   "#"
@@ -21064,7 +21064,7 @@
          (unspec:VI1_AVX512
            [(match_operand:VI1_AVX512 1 "register_operand" "v")
             (match_operand:VI1_AVX512 2 "nonimmediate_operand" "vm")
-            (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
+            (match_operand:SI 3 "const_0_to_255_mul_8_operand")]
            UNSPEC_PALIGNR)
        (match_operand:VI1_AVX512 4 "nonimm_or_0_operand" "0C")
        (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
@@ -21085,7 +21085,7 @@
        (unspec:SSESCALARMODE
          [(match_operand:SSESCALARMODE 1 "register_operand" "0,<v_Yw>")
           (match_operand:SSESCALARMODE 2 "vector_operand" "xBm,<v_Yw>m")
-          (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n")]
+          (match_operand:SI 3 "const_0_to_255_mul_8_operand")]
          UNSPEC_PALIGNR))]
   "TARGET_SSSE3"
 {
@@ -21114,7 +21114,7 @@
   [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
        (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
                    (match_operand:DI 2 "register_mmxmem_operand" "ym,x,Yv")
-                   (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n,n,n")]
+                   (match_operand:SI 3 "const_0_to_255_mul_8_operand")]
                   UNSPEC_PALIGNR))]
   "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"
 {
@@ -21401,7 +21401,7 @@
           (match_operand:VF_128_256 2 "vector_operand" "YrBm,*xBm,xm")
           (lt:VF_128_256
             (match_operand:<sseintvecmode> 3 "register_operand" "Yz,Yz,x")
-            (match_operand:<sseintvecmode> 4 "const0_operand" "C,C,C"))]
+            (match_operand:<sseintvecmode> 4 "const0_operand"))]
          UNSPEC_BLENDV))]
   "TARGET_SSE4_1"
   "#"
@@ -21433,7 +21433,7 @@
           (subreg:<ssebytemode>
             (lt:VI48_AVX
               (match_operand:VI48_AVX 3 "register_operand" "Yz,Yz,x")
-              (match_operand:VI48_AVX 4 "const0_operand" "C,C,C")) 0)]
+              (match_operand:VI48_AVX 4 "const0_operand")) 0)]
          UNSPEC_BLENDV))]
   "TARGET_SSE4_1"
   "#"
@@ -21488,7 +21488,7 @@
        (unspec:VF_128_256
          [(match_operand:VF_128_256 1 "vector_operand" "%0,0,x")
           (match_operand:VF_128_256 2 "vector_operand" "YrBm,*xBm,xm")
-          (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")]
+          (match_operand:SI 3 "const_0_to_255_operand")]
          UNSPEC_DP))]
   "TARGET_SSE4_1"
   "@
@@ -21526,7 +21526,7 @@
        (unspec:VI1_AVX2
          [(match_operand:VI1_AVX2 1 "register_operand" "0,0,x")
           (match_operand:VI1_AVX2 2 "vector_operand" "YrBm,*xBm,xm")
-          (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")]
+          (match_operand:SI 3 "const_0_to_255_operand")]
          UNSPEC_MPSADBW))]
   "TARGET_SSE4_1"
   "@
@@ -21615,7 +21615,7 @@
          [(match_operand:VI1_AVX2 1 "register_operand"  "0,0,x")
           (match_operand:VI1_AVX2 2 "vector_operand" "YrBm,*xBm,xm")
           (lt:VI1_AVX2 (match_operand:VI1_AVX2 3 "register_operand" "Yz,Yz,x")
-                       (match_operand:VI1_AVX2 4 "const0_operand" "C,C,C"))]
+                       (match_operand:VI1_AVX2 4 "const0_operand"))]
          UNSPEC_BLENDV))]
   "TARGET_SSE4_1"
   "#"
@@ -21659,7 +21659,7 @@
        (vec_merge:V8_128
          (match_operand:V8_128 2 "vector_operand" "YrBm,*xBm,xm")
          (match_operand:V8_128 1 "register_operand" "0,0,x")
-         (match_operand:SI 3 "const_0_to_255_operand" "n,n,n")))]
+         (match_operand:SI 3 "const_0_to_255_operand")))]
   "TARGET_SSE4_1"
   "@
    pblendw\t{%3, %2, %0|%0, %2, %3}
@@ -21731,7 +21731,7 @@
        (vec_merge:V16_256
          (match_operand:V16_256 2 "nonimmediate_operand" "xm")
          (match_operand:V16_256 1 "register_operand" "x")
-         (match_operand:SI 3 "avx2_pblendw_operand" "n")))]
+         (match_operand:SI 3 "avx2_pblendw_operand")))]
   "TARGET_AVX2"
 {
   operands[3] = GEN_INT (INTVAL (operands[3]) & 0xff);
@@ -21748,7 +21748,7 @@
        (vec_merge:VI4_AVX2
          (match_operand:VI4_AVX2 2 "nonimmediate_operand" "xm")
          (match_operand:VI4_AVX2 1 "register_operand" "x")
-         (match_operand:SI 3 "const_0_to_255_operand" "n")))]
+         (match_operand:SI 3 "const_0_to_255_operand")))]
   "TARGET_AVX2"
   "vpblendd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
   [(set_attr "type" "ssemov")
@@ -21785,9 +21785,9 @@
        (vec_select:V32QI
          (vec_concat:V64QI
            (match_operand:V32QI 1 "nonimmediate_operand" "vm")
-           (match_operand:V32QI 2 "const0_operand" "C"))
+           (match_operand:V32QI 2 "const0_operand"))
          (match_parallel 3 "pmovzx_parallel"
-           [(match_operand 4 "const_int_operand" "n")])))]
+           [(match_operand 4 "const_int_operand")])))]
   "TARGET_AVX2"
   "#"
   "&& reload_completed"
@@ -21804,10 +21804,10 @@
            (subreg:V32QI
              (vec_concat:VI248_256
                (match_operand:<ssehalfvecmode> 1 "nonimmediate_operand" "vm")
-               (match_operand:<ssehalfvecmode> 2 "const0_operand" "C")) 0)
-           (match_operand:V32QI 3 "const0_operand" "C"))
+               (match_operand:<ssehalfvecmode> 2 "const0_operand")) 0)
+           (match_operand:V32QI 3 "const0_operand"))
          (match_parallel 4 "pmovzx_parallel"
-           [(match_operand 5 "const_int_operand" "n")])))]
+           [(match_operand 5 "const_int_operand")])))]
   "TARGET_AVX2"
   "#"
   "&& reload_completed"
@@ -21839,9 +21839,9 @@
        (vec_select:V64QI
          (vec_concat:V128QI
            (match_operand:V64QI 1 "nonimmediate_operand" "vm")
-           (match_operand:V64QI 2 "const0_operand" "C"))
+           (match_operand:V64QI 2 "const0_operand"))
          (match_parallel 3 "pmovzx_parallel"
-           [(match_operand 4 "const_int_operand" "n")])))]
+           [(match_operand 4 "const_int_operand")])))]
   "TARGET_AVX512BW"
   "#"
   "&& reload_completed"
@@ -21858,10 +21858,10 @@
            (subreg:V64QI
              (vec_concat:VI248_512
                (match_operand:<ssehalfvecmode> 1 "nonimmediate_operand" "vm")
-               (match_operand:<ssehalfvecmode> 2 "const0_operand" "C")) 0)
-           (match_operand:V64QI 3 "const0_operand" "C"))
+               (match_operand:<ssehalfvecmode> 2 "const0_operand")) 0)
+           (match_operand:V64QI 3 "const0_operand"))
          (match_parallel 4 "pmovzx_parallel"
-           [(match_operand 5 "const_int_operand" "n")])))]
+           [(match_operand 5 "const_int_operand")])))]
   "TARGET_AVX512BW"
   "#"
   "&& reload_completed"
@@ -21931,9 +21931,9 @@
        (vec_select:V16QI
          (vec_concat:V32QI
            (match_operand:V16QI 1 "vector_operand" "YrBm,*xBm,Ywm")
-           (match_operand:V16QI 2 "const0_operand" "C,C,C"))
+           (match_operand:V16QI 2 "const0_operand"))
          (match_parallel 3 "pmovzx_parallel"
-           [(match_operand 4 "const_int_operand" "n,n,n")])))]
+           [(match_operand 4 "const_int_operand")])))]
   "TARGET_SSE4_1"
   "#"
   "&& reload_completed"
@@ -21964,10 +21964,10 @@
            (subreg:V16QI
              (vec_concat:VI248_128
                (match_operand:<ssehalfvecmode> 1 "vector_operand" "YrBm,*xBm,Ywm")
-               (match_operand:<ssehalfvecmode> 2 "const0_operand" "C,C,C")) 0)
-           (match_operand:V16QI 3 "const0_operand" "C,C,C"))
+               (match_operand:<ssehalfvecmode> 2 "const0_operand")) 0)
+           (match_operand:V16QI 3 "const0_operand"))
          (match_parallel 4 "pmovzx_parallel"
-           [(match_operand 5 "const_int_operand" "n,n,n")])))]
+           [(match_operand 5 "const_int_operand")])))]
   "TARGET_SSE4_1"
   "#"
   "&& reload_completed"
@@ -22170,9 +22170,9 @@
        (vec_select:V32HI
          (vec_concat:V64HI
            (match_operand:V32HI 1 "nonimmediate_operand" "vm")
-           (match_operand:V32HI 2 "const0_operand" "C"))
+           (match_operand:V32HI 2 "const0_operand"))
          (match_parallel 3 "pmovzx_parallel"
-           [(match_operand 4 "const_int_operand" "n")])))]
+           [(match_operand 4 "const_int_operand")])))]
   "TARGET_AVX512F"
   "#"
   "&& reload_completed"
@@ -22189,10 +22189,10 @@
            (subreg:V32HI
              (vec_concat:VI148_512
                (match_operand:<ssehalfvecmode> 1 "nonimmediate_operand" "vm")
-               (match_operand:<ssehalfvecmode> 2 "const0_operand" "C")) 0)
-           (match_operand:V32HI 3 "const0_operand" "C"))
+               (match_operand:<ssehalfvecmode> 2 "const0_operand")) 0)
+           (match_operand:V32HI 3 "const0_operand"))
          (match_parallel 4 "pmovzx_parallel"
-           [(match_operand 5 "const_int_operand" "n")])))]
+           [(match_operand 5 "const_int_operand")])))]
   "TARGET_AVX512F"
   "#"
   "&& reload_completed"
@@ -22224,9 +22224,9 @@
        (vec_select:V16HI
          (vec_concat:V32HI
            (match_operand:V16HI 1 "nonimmediate_operand" "vm")
-           (match_operand:V16HI 2 "const0_operand" "C"))
+           (match_operand:V16HI 2 "const0_operand"))
          (match_parallel 3 "pmovzx_parallel"
-           [(match_operand 4 "const_int_operand" "n")])))]
+           [(match_operand 4 "const_int_operand")])))]
   "TARGET_AVX2"
   "#"
   "&& reload_completed"
@@ -22243,10 +22243,10 @@
            (subreg:V16HI
              (vec_concat:VI148_256
                (match_operand:<ssehalfvecmode> 1 "nonimmediate_operand" "vm")
-               (match_operand:<ssehalfvecmode> 2 "const0_operand" "C")) 0)
-           (match_operand:V16HI 3 "const0_operand" "C"))
+               (match_operand:<ssehalfvecmode> 2 "const0_operand")) 0)
+           (match_operand:V16HI 3 "const0_operand"))
          (match_parallel 4 "pmovzx_parallel"
-           [(match_operand 5 "const_int_operand" "n")])))]
+           [(match_operand 5 "const_int_operand")])))]
   "TARGET_AVX2"
   "#"
   "&& reload_completed"
@@ -22322,9 +22322,9 @@
        (vec_select:V8HI
          (vec_concat:V16HI
            (match_operand:V8HI 1 "vector_operand" "YrBm,*xBm,vm")
-           (match_operand:V8HI 2 "const0_operand" "C,C,C"))
+           (match_operand:V8HI 2 "const0_operand"))
          (match_parallel 3 "pmovzx_parallel"
-           [(match_operand 4 "const_int_operand" "n,n,n")])))]
+           [(match_operand 4 "const_int_operand")])))]
   "TARGET_SSE4_1"
   "#"
   "&& reload_completed"
@@ -22353,10 +22353,10 @@
            (subreg:V8HI
              (vec_concat:VI148_128
                (match_operand:<ssehalfvecmode> 1 "vector_operand" "YrBm,*xBm,vm")
-               (match_operand:<ssehalfvecmode> 2 "const0_operand" "C,C,C")) 0)
-           (match_operand:V8HI 3 "const0_operand" "C,C,C"))
+               (match_operand:<ssehalfvecmode> 2 "const0_operand")) 0)
+           (match_operand:V8HI 3 "const0_operand"))
          (match_parallel 4 "pmovzx_parallel"
-           [(match_operand 5 "const_int_operand" "n,n,n")])))]
+           [(match_operand 5 "const_int_operand")])))]
   "TARGET_SSE4_1"
   "#"
   "&& reload_completed"
@@ -22714,9 +22714,9 @@
        (vec_select:V16SI
          (vec_concat:V32SI
            (match_operand:V16SI 1 "nonimmediate_operand" "vm")
-           (match_operand:V16SI 2 "const0_operand" "C"))
+           (match_operand:V16SI 2 "const0_operand"))
          (match_parallel 3 "pmovzx_parallel"
-           [(match_operand 4 "const_int_operand" "n")])))]
+           [(match_operand 4 "const_int_operand")])))]
   "TARGET_AVX512F"
   "#"
   "&& reload_completed"
@@ -22732,10 +22732,10 @@
          (vec_concat:V32SI
            (vec_concat:V16SI
              (match_operand:V8SI 1 "nonimmediate_operand" "vm")
-             (match_operand:V8SI 2 "const0_operand" "C"))
-           (match_operand:V16SI 3 "const0_operand" "C"))
+             (match_operand:V8SI 2 "const0_operand"))
+           (match_operand:V16SI 3 "const0_operand"))
          (match_parallel 4 "pmovzx_parallel"
-           [(match_operand 5 "const_int_operand" "n")])))]
+           [(match_operand 5 "const_int_operand")])))]
   "TARGET_AVX512F"
   "#"
   "&& reload_completed"
@@ -22766,9 +22766,9 @@
        (vec_select:V8SI
          (vec_concat:V16SI
            (match_operand:V8SI 1 "nonimmediate_operand" "vm")
-           (match_operand:V8SI 2 "const0_operand" "C"))
+           (match_operand:V8SI 2 "const0_operand"))
          (match_parallel 3 "pmovzx_parallel"
-           [(match_operand 4 "const_int_operand" "n")])))]
+           [(match_operand 4 "const_int_operand")])))]
   "TARGET_AVX2"
   "#"
   "&& reload_completed"
@@ -22784,10 +22784,10 @@
          (vec_concat:V16SI
            (vec_concat:V8SI
              (match_operand:V4SI 1 "nonimmediate_operand" "vm")
-             (match_operand:V4SI 2 "const0_operand" "C"))
-           (match_operand:V8SI 3 "const0_operand" "C"))
+             (match_operand:V4SI 2 "const0_operand"))
+           (match_operand:V8SI 3 "const0_operand"))
          (match_parallel 4 "pmovzx_parallel"
-           [(match_operand 5 "const_int_operand" "n")])))]
+           [(match_operand 5 "const_int_operand")])))]
   "TARGET_AVX2"
   "#"
   "&& reload_completed"
@@ -22850,9 +22850,9 @@
        (vec_select:V4SI
          (vec_concat:V8SI
            (match_operand:V4SI 1 "vector_operand" "YrBm,*xBm,vm")
-           (match_operand:V4SI 2 "const0_operand" "C,C,C"))
+           (match_operand:V4SI 2 "const0_operand"))
          (match_parallel 3 "pmovzx_parallel"
-           [(match_operand 4 "const_int_operand" "n,n,n")])))]
+           [(match_operand 4 "const_int_operand")])))]
   "TARGET_SSE4_1"
   "#"
   "&& reload_completed"
@@ -22878,10 +22878,10 @@
          (vec_concat:V8SI
            (vec_concat:V4SI
              (match_operand:V2SI 1 "vector_operand" "YrBm, *xBm, vm")
-             (match_operand:V2SI 2 "const0_operand" "C,C,C"))
-           (match_operand:V4SI 3 "const0_operand" "C,C,C"))
+             (match_operand:V2SI 2 "const0_operand"))
+           (match_operand:V4SI 3 "const0_operand"))
          (match_parallel 4 "pmovzx_parallel"
-           [(match_operand 5 "const_int_operand" "n,n,n")])))]
+           [(match_operand 5 "const_int_operand")])))]
   "TARGET_SSE4_1"
   "#"
   "&& reload_completed"
@@ -22985,7 +22985,7 @@
   [(set (match_operand:VF_128_256 0 "register_operand" "=Yr,*x,x")
        (unspec:VF_128_256
          [(match_operand:VF_128_256 1 "vector_operand" "YrBm,*xBm,xm")
-          (match_operand:SI 2 "const_0_to_15_operand" "n,n,n")]
+          (match_operand:SI 2 "const_0_to_15_operand")]
          UNSPEC_ROUND))]
   "TARGET_SSE4_1"
   "%vround<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
@@ -23078,7 +23078,7 @@
        (vec_merge:VF_128
          (unspec:VF_128
            [(match_operand:VF_128 2 "nonimmediate_operand" "Yrm,*xm,xm,vm")
-            (match_operand:SI 3 "const_0_to_15_operand" "n,n,n,n")]
+            (match_operand:SI 3 "const_0_to_15_operand")]
            UNSPEC_ROUND)
          (match_operand:VF_128 1 "register_operand" "0,0,x,v")
          (const_int 1)))]
@@ -23102,7 +23102,7 @@
          (vec_duplicate:VFH_128
            (unspec:<ssescalarmode>
              [(match_operand:<ssescalarmode> 2 "nonimmediate_operand" "Yrm,*xm,xm,vm")
-              (match_operand:SI 3 "const_0_to_15_operand" "n,n,n,n")]
+              (match_operand:SI 3 "const_0_to_15_operand")]
              UNSPEC_ROUND))
          (match_operand:VFH_128 1 "register_operand" "0,0,x,v")
          (const_int 1)))]
@@ -23215,7 +23215,7 @@
           (match_operand:SI 3 "register_operand" "a,a")
           (match_operand:V16QI 4 "nonimmediate_operand" "x,m")
           (match_operand:SI 5 "register_operand" "d,d")
-          (match_operand:SI 6 "const_0_to_255_operand" "n,n")]
+          (match_operand:SI 6 "const_0_to_255_operand")]
          UNSPEC_PCMPESTR))
    (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
        (unspec:V16QI
@@ -23275,7 +23275,7 @@
           (match_operand:SI 2 "register_operand" "a,a")
           (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
           (match_operand:SI 4 "register_operand" "d,d")
-          (match_operand:SI 5 "const_0_to_255_operand" "n,n")]
+          (match_operand:SI 5 "const_0_to_255_operand")]
          UNSPEC_PCMPESTR))
    (set (reg:CC FLAGS_REG)
        (unspec:CC
@@ -23303,7 +23303,7 @@
           (match_operand:SI 2 "register_operand" "a,a")
           (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
           (match_operand:SI 4 "register_operand" "d,d")
-          (match_operand:SI 5 "const_0_to_255_operand" "n,n")]
+          (match_operand:SI 5 "const_0_to_255_operand")]
          UNSPEC_PCMPESTR))
    (set (reg:CC FLAGS_REG)
        (unspec:CC
@@ -23331,7 +23331,7 @@
           (match_operand:SI 3 "register_operand" "a,a,a,a")
           (match_operand:V16QI 4 "nonimmediate_operand" "x,m,x,m")
           (match_operand:SI 5 "register_operand" "d,d,d,d")
-          (match_operand:SI 6 "const_0_to_255_operand" "n,n,n,n")]
+          (match_operand:SI 6 "const_0_to_255_operand")]
          UNSPEC_PCMPESTR))
    (clobber (match_scratch:V16QI 0 "=Yz,Yz,X,X"))
    (clobber (match_scratch:SI    1 "= X, X,c,c"))]
@@ -23355,7 +23355,7 @@
        (unspec:SI
          [(match_operand:V16QI 2 "register_operand" "x,x")
           (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
-          (match_operand:SI 4 "const_0_to_255_operand" "n,n")]
+          (match_operand:SI 4 "const_0_to_255_operand")]
          UNSPEC_PCMPISTR))
    (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
        (unspec:V16QI
@@ -23406,7 +23406,7 @@
        (unspec:SI
          [(match_operand:V16QI 1 "register_operand" "x,x")
           (match_operand:V16QI 2 "nonimmediate_operand" "x,m")
-          (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
+          (match_operand:SI 3 "const_0_to_255_operand")]
          UNSPEC_PCMPISTR))
    (set (reg:CC FLAGS_REG)
        (unspec:CC
@@ -23430,7 +23430,7 @@
        (unspec:V16QI
          [(match_operand:V16QI 1 "register_operand" "x,x")
           (match_operand:V16QI 2 "nonimmediate_operand" "x,m")
-          (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
+          (match_operand:SI 3 "const_0_to_255_operand")]
          UNSPEC_PCMPISTR))
    (set (reg:CC FLAGS_REG)
        (unspec:CC
@@ -23454,7 +23454,7 @@
        (unspec:CC
          [(match_operand:V16QI 2 "register_operand" "x,x,x,x")
           (match_operand:V16QI 3 "nonimmediate_operand" "x,m,x,m")
-          (match_operand:SI 4 "const_0_to_255_operand" "n,n,n,n")]
+          (match_operand:SI 4 "const_0_to_255_operand")]
          UNSPEC_PCMPISTR))
    (clobber (match_scratch:V16QI 0 "=Yz,Yz,X,X"))
    (clobber (match_scratch:SI    1 "= X, X,c,c"))]
@@ -23501,9 +23501,9 @@
        [(unspec:P
           [(match_operand:P 2 "vsib_address_operand" "Tv")
            (match_operand:VI48_512 1 "register_operand" "v")
-           (match_operand:SI 3 "const1248_operand" "n")]
+           (match_operand:SI 3 "const1248_operand")]
           UNSPEC_VSIBADDR)])
-      (match_operand:SI 4 "const_2_to_3_operand" "n")]
+      (match_operand:SI 4 "const_2_to_3_operand")]
      UNSPEC_GATHER_PREFETCH)]
   "TARGET_AVX512PF"
 {
@@ -23548,9 +23548,9 @@
        [(unspec:P
           [(match_operand:P 2 "vsib_address_operand" "Tv")
            (match_operand:VI4_256_8_512 1 "register_operand" "v")
-           (match_operand:SI 3 "const1248_operand" "n")]
+           (match_operand:SI 3 "const1248_operand")]
           UNSPEC_VSIBADDR)])
-      (match_operand:SI 4 "const_2_to_3_operand" "n")]
+      (match_operand:SI 4 "const_2_to_3_operand")]
      UNSPEC_GATHER_PREFETCH)]
   "TARGET_AVX512PF"
 {
@@ -23595,9 +23595,9 @@
        [(unspec:P
           [(match_operand:P 2 "vsib_address_operand" "Tv")
            (match_operand:VI48_512 1 "register_operand" "v")
-           (match_operand:SI 3 "const1248_operand" "n")]
+           (match_operand:SI 3 "const1248_operand")]
           UNSPEC_VSIBADDR)])
-      (match_operand:SI 4 "const2367_operand" "n")]
+      (match_operand:SI 4 "const2367_operand")]
      UNSPEC_SCATTER_PREFETCH)]
   "TARGET_AVX512PF"
 {
@@ -23644,9 +23644,9 @@
        [(unspec:P
           [(match_operand:P 2 "vsib_address_operand" "Tv")
            (match_operand:VI4_256_8_512 1 "register_operand" "v")
-           (match_operand:SI 3 "const1248_operand" "n")]
+           (match_operand:SI 3 "const1248_operand")]
           UNSPEC_VSIBADDR)])
-      (match_operand:SI 4 "const2367_operand" "n")]
+      (match_operand:SI 4 "const2367_operand")]
      UNSPEC_SCATTER_PREFETCH)]
   "TARGET_AVX512PF"
 {
@@ -24184,7 +24184,7 @@
   [(set (match_operand:VI_128 0 "register_operand" "=x")
        (rotate:VI_128
         (match_operand:VI_128 1 "nonimmediate_operand" "xm")
-        (match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
+        (match_operand:SI 2 "const_0_to_<sserotatemax>_operand")))]
   "TARGET_XOP"
   "vprot<ssemodesuffix>\t{%2, %1, %0|%0, %1, %2}"
   [(set_attr "type" "sseishft")
@@ -24195,7 +24195,7 @@
   [(set (match_operand:VI_128 0 "register_operand" "=x")
        (rotatert:VI_128
         (match_operand:VI_128 1 "nonimmediate_operand" "xm")
-        (match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
+        (match_operand:SI 2 "const_0_to_<sserotatemax>_operand")))]
   "TARGET_XOP"
 {
   operands[3]
@@ -24802,7 +24802,7 @@
        (unspec:VI_128
          [(match_operand:VI_128 1 "register_operand" "x")
           (match_operand:VI_128 2 "nonimmediate_operand" "xm")
-          (match_operand:SI 3 "const_int_operand" "n")]
+          (match_operand:SI 3 "const_int_operand")]
          UNSPEC_XOP_TRUEFALSE))]
   "TARGET_XOP"
 {
@@ -24822,7 +24822,7 @@
          [(match_operand:VF_128_256 1 "register_operand" "x,x")
           (match_operand:VF_128_256 2 "nonimmediate_operand" "x,m")
           (match_operand:<sseintvecmode> 3 "nonimmediate_operand" "xm,x")
-          (match_operand:SI 4 "const_0_to_3_operand" "n,n")]
+          (match_operand:SI 4 "const_0_to_3_operand")]
          UNSPEC_VPERMIL2))]
   "TARGET_XOP"
   "vpermil2<ssemodesuffix>\t{%4, %3, %2, %1, %0|%0, %1, %2, %3, %4}"
@@ -24910,7 +24910,7 @@
 (define_insn "aeskeygenassist"
   [(set (match_operand:V2DI 0 "register_operand" "=x")
        (unspec:V2DI [(match_operand:V2DI 1 "vector_operand" "xBm")
-                     (match_operand:SI 2 "const_0_to_255_operand" "n")]
+                     (match_operand:SI 2 "const_0_to_255_operand")]
                     UNSPEC_AESKEYGENASSIST))]
   "TARGET_AES"
   "%vaeskeygenassist\t{%2, %1, %0|%0, %1, %2}"
@@ -24924,7 +24924,7 @@
   [(set (match_operand:V2DI 0 "register_operand" "=x,x")
        (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0,x")
                      (match_operand:V2DI 2 "vector_operand" "xBm,xm")
-                     (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
+                     (match_operand:SI 3 "const_0_to_255_operand")]
                     UNSPEC_PCLMUL))]
   "TARGET_PCLMUL"
   "@
@@ -25376,7 +25376,7 @@
        (unspec:V4DI
          [(match_operand:V4DI 1 "register_operand" "x")
           (match_operand:V4DI 2 "nonimmediate_operand" "xm")
-          (match_operand:SI 3 "const_0_to_255_operand" "n")]
+          (match_operand:SI 3 "const_0_to_255_operand")]
          UNSPEC_VPERMTI))]
   "TARGET_AVX2"
   "vperm2i128\t{%3, %2, %1, %0|%0, %1, %2, %3}"
@@ -25920,7 +25920,7 @@
        (unspec:AVX256MODE2P
          [(match_operand:AVX256MODE2P 1 "register_operand" "x")
           (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "xm")
-          (match_operand:SI 3 "const_0_to_255_operand" "n")]
+          (match_operand:SI 3 "const_0_to_255_operand")]
          UNSPEC_VPERMIL2F128))]
   "TARGET_AVX"
   "vperm2<i128>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
@@ -25960,7 +25960,7 @@
       (vec_select:V_128
        (match_operand:V_128 1 "register_operand" "0,Yw")
        (match_parallel 2 "palignr_operand"
-         [(match_operand 3 "const_int_operand" "n,n")])))]
+         [(match_operand 3 "const_int_operand")])))]
   "TARGET_SSSE3"
 {
   operands[2] = (GEN_INT (INTVAL (operands[3])
@@ -26630,7 +26630,7 @@
   [(set (match_operand:V8HI 0 "register_operand" "=v")
        (vec_concat:V8HI
          (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "v")
-                       (match_operand:SI 2 "const_0_to_255_operand" "N")]
+                       (match_operand:SI 2 "const_0_to_255_operand")]
                       UNSPEC_VCVTPS2PH)
          (match_operand:V4HI 3 "const0_operand")))]
   "(TARGET_F16C || TARGET_AVX512VL) && <mask_avx512vl_condition>"
@@ -26642,7 +26642,7 @@
 (define_insn "*vcvtps2ph_store<merge_mask_name>"
   [(set (match_operand:V4HI 0 "memory_operand" "=m")
        (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "v")
-                     (match_operand:SI 2 "const_0_to_255_operand" "N")]
+                     (match_operand:SI 2 "const_0_to_255_operand")]
                     UNSPEC_VCVTPS2PH))]
   "TARGET_F16C || TARGET_AVX512VL"
   "vcvtps2ph\t{%2, %1, %0<merge_mask_operand3>|%0<merge_mask_operand3>, %1, %2}"
@@ -26653,7 +26653,7 @@
 (define_insn "vcvtps2ph256<mask_name>"
   [(set (match_operand:V8HI 0 "register_operand" "=v")
        (unspec:V8HI [(match_operand:V8SF 1 "register_operand" "v")
-                     (match_operand:SI 2 "const_0_to_255_operand" "N")]
+                     (match_operand:SI 2 "const_0_to_255_operand")]
                     UNSPEC_VCVTPS2PH))]
   "TARGET_F16C || TARGET_AVX512VL"
   "vcvtps2ph\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -26665,7 +26665,7 @@
 (define_insn "*vcvtps2ph256<merge_mask_name>"
   [(set (match_operand:V8HI 0 "memory_operand" "=m")
        (unspec:V8HI [(match_operand:V8SF 1 "register_operand" "v")
-                     (match_operand:SI 2 "const_0_to_255_operand" "N")]
+                     (match_operand:SI 2 "const_0_to_255_operand")]
                     UNSPEC_VCVTPS2PH))]
   "TARGET_F16C || TARGET_AVX512VL"
   "vcvtps2ph\t{%2, %1, %0<merge_mask_operand3>|%0<merge_mask_operand3>, %1, %2}"
@@ -26678,7 +26678,7 @@
   [(set (match_operand:V16HI 0 "register_operand" "=v")
        (unspec:V16HI
          [(match_operand:V16SF 1 "register_operand" "v")
-          (match_operand:SI 2 "const_0_to_255_operand" "N")]
+          (match_operand:SI 2 "const_0_to_255_operand")]
          UNSPEC_VCVTPS2PH))]
   "TARGET_AVX512F"
   "vcvtps2ph\t{%2, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2}"
@@ -26690,7 +26690,7 @@
   [(set (match_operand:V16HI 0 "memory_operand" "=m")
        (unspec:V16HI
          [(match_operand:V16SF 1 "register_operand" "v")
-          (match_operand:SI 2 "const_0_to_255_operand" "N")]
+          (match_operand:SI 2 "const_0_to_255_operand")]
          UNSPEC_VCVTPS2PH))]
   "TARGET_AVX512F"
   "vcvtps2ph\t{%2, %1, %0<merge_mask_operand3>|%0<merge_mask_operand3>, %1, %2}"
@@ -26748,7 +26748,7 @@
             [(unspec:P
                [(match_operand:P 3 "vsib_address_operand" "Tv")
                 (match_operand:<VEC_GATHER_IDXSI> 4 "register_operand" "x")
-                (match_operand:SI 6 "const1248_operand" "n")]
+                (match_operand:SI 6 "const1248_operand")]
                UNSPEC_VSIBADDR)])
           (mem:BLK (scratch))
           (match_operand:VEC_GATHER_MODE 5 "register_operand" "1")]
@@ -26768,7 +26768,7 @@
             [(unspec:P
                [(match_operand:P 2 "vsib_address_operand" "Tv")
                 (match_operand:<VEC_GATHER_IDXSI> 3 "register_operand" "x")
-                (match_operand:SI 5 "const1248_operand" "n")]
+                (match_operand:SI 5 "const1248_operand")]
                UNSPEC_VSIBADDR)])
           (mem:BLK (scratch))
           (match_operand:VEC_GATHER_MODE 4 "register_operand" "1")]
@@ -26809,7 +26809,7 @@
             [(unspec:P
                [(match_operand:P 3 "vsib_address_operand" "Tv")
                 (match_operand:<VEC_GATHER_IDXDI> 4 "register_operand" "x")
-                (match_operand:SI 6 "const1248_operand" "n")]
+                (match_operand:SI 6 "const1248_operand")]
                UNSPEC_VSIBADDR)])
           (mem:BLK (scratch))
           (match_operand:<VEC_GATHER_SRCDI> 5 "register_operand" "1")]
@@ -26829,7 +26829,7 @@
             [(unspec:P
                [(match_operand:P 2 "vsib_address_operand" "Tv")
                 (match_operand:<VEC_GATHER_IDXDI> 3 "register_operand" "x")
-                (match_operand:SI 5 "const1248_operand" "n")]
+                (match_operand:SI 5 "const1248_operand")]
                UNSPEC_VSIBADDR)])
           (mem:BLK (scratch))
           (match_operand:<VEC_GATHER_SRCDI> 4 "register_operand" "1")]
@@ -26854,7 +26854,7 @@
               [(unspec:P
                  [(match_operand:P 3 "vsib_address_operand" "Tv")
                   (match_operand:<VEC_GATHER_IDXDI> 4 "register_operand" "x")
-                  (match_operand:SI 6 "const1248_operand" "n")]
+                  (match_operand:SI 6 "const1248_operand")]
                  UNSPEC_VSIBADDR)])
             (mem:BLK (scratch))
             (match_operand:<VEC_GATHER_SRCDI> 5 "register_operand" "1")]
@@ -26877,7 +26877,7 @@
               [(unspec:P
                  [(match_operand:P 2 "vsib_address_operand" "Tv")
                   (match_operand:<VEC_GATHER_IDXDI> 3 "register_operand" "x")
-                  (match_operand:SI 5 "const1248_operand" "n")]
+                  (match_operand:SI 5 "const1248_operand")]
                  UNSPEC_VSIBADDR)])
             (mem:BLK (scratch))
             (match_operand:<VEC_GATHER_SRCDI> 4 "register_operand" "1")]
@@ -26919,7 +26919,7 @@
             [(unspec:P
                [(match_operand:P 4 "vsib_address_operand" "Tv")
                 (match_operand:<VEC_GATHER_IDXSI> 3 "register_operand" "v")
-                (match_operand:SI 5 "const1248_operand" "n")]
+                (match_operand:SI 5 "const1248_operand")]
                UNSPEC_VSIBADDR)])]
          UNSPEC_GATHER))
    (clobber (match_scratch:<avx512fmaskmode> 2 "=&Yk"))]
@@ -26940,7 +26940,7 @@
             [(unspec:P
                [(match_operand:P 3 "vsib_address_operand" "Tv")
                 (match_operand:<VEC_GATHER_IDXSI> 2 "register_operand" "v")
-                (match_operand:SI 4 "const1248_operand" "n")]
+                (match_operand:SI 4 "const1248_operand")]
                UNSPEC_VSIBADDR)])]
          UNSPEC_GATHER))
    (clobber (match_scratch:<avx512fmaskmode> 1 "=&Yk"))]
@@ -26981,7 +26981,7 @@
             [(unspec:P
                [(match_operand:P 4 "vsib_address_operand" "Tv")
                 (match_operand:<VEC_GATHER_IDXDI> 3 "register_operand" "v")
-                (match_operand:SI 5 "const1248_operand" "n")]
+                (match_operand:SI 5 "const1248_operand")]
                UNSPEC_VSIBADDR)])]
          UNSPEC_GATHER))
    (clobber (match_scratch:QI 2 "=&Yk"))]
@@ -27002,7 +27002,7 @@
             [(unspec:P
                [(match_operand:P 3 "vsib_address_operand" "Tv")
                 (match_operand:<VEC_GATHER_IDXDI> 2 "register_operand" "v")
-                (match_operand:SI 4 "const1248_operand" "n")]
+                (match_operand:SI 4 "const1248_operand")]
                UNSPEC_VSIBADDR)])]
          UNSPEC_GATHER))
    (clobber (match_scratch:QI 1 "=&Yk"))]
@@ -27047,7 +27047,7 @@
          [(unspec:P
             [(match_operand:P 0 "vsib_address_operand" "Tv")
              (match_operand:<VEC_GATHER_IDXSI> 2 "register_operand" "v")
-             (match_operand:SI 4 "const1248_operand" "n")
+             (match_operand:SI 4 "const1248_operand")
              (match_operand:<avx512fmaskmode> 6 "register_operand" "1")]
             UNSPEC_VSIBADDR)])
        (unspec:VI48F
@@ -27087,7 +27087,7 @@
          [(unspec:P
             [(match_operand:P 0 "vsib_address_operand" "Tv")
              (match_operand:<VEC_GATHER_IDXDI> 2 "register_operand" "v")
-             (match_operand:SI 4 "const1248_operand" "n")
+             (match_operand:SI 4 "const1248_operand")
              (match_operand:QI 6 "register_operand" "1")]
             UNSPEC_VSIBADDR)])
        (unspec:VI48F
@@ -27308,7 +27308,7 @@
   [(set (match_operand:<avx512fmaskmode> 0 "register_operand" "=k")
           (unspec:<avx512fmaskmode>
             [(match_operand:VFH_AVX512VL 1 "vector_operand" "vm")
-             (match_operand 2 "const_0_to_255_operand" "n")]
+             (match_operand 2 "const_0_to_255_operand")]
              UNSPEC_FPCLASS))]
    "TARGET_AVX512DQ || VALID_AVX512FP16_REG_MODE(<MODE>mode)"
    "vfpclass<ssemodesuffix><vecmemsuffix>\t{%2, %1, %0<mask_scalar_merge_operand3>|%0<mask_scalar_merge_operand3>, %1, %2}";
@@ -27322,7 +27322,7 @@
        (and:<avx512fmaskmode>
          (unspec:<avx512fmaskmode>
            [(match_operand:VFH_128 1 "nonimmediate_operand" "vm")
-             (match_operand 2 "const_0_to_255_operand" "n")]
+             (match_operand 2 "const_0_to_255_operand")]
            UNSPEC_FPCLASS)
          (const_int 1)))]
    "TARGET_AVX512DQ || VALID_AVX512FP16_REG_MODE(<MODE>mode)"
@@ -27446,7 +27446,7 @@
        (unspec:V4SI
          [(match_operand:V4SI 1 "register_operand" "0")
           (match_operand:V4SI 2 "vector_operand" "xBm")
-          (match_operand:SI 3 "const_0_to_3_operand" "n")]
+          (match_operand:SI 3 "const_0_to_3_operand")]
          UNSPEC_SHA1RNDS4))]
   "TARGET_SHA"
   "sha1rnds4\t{%3, %2, %0|%0, %2, %3}"
@@ -27673,7 +27673,7 @@
            [(match_operand:V16SF 1 "register_operand" "0")
             (match_operand:V64SF 2 "register_operand" "v")
             (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD)
-         (match_operand:V16SF 4 "const0_operand" "C")
+         (match_operand:V16SF 4 "const0_operand")
          (match_operand:HI 5 "register_operand" "Yk")))]
   "TARGET_AVX5124FMAPS"
   "v4fmaddps\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
@@ -27714,7 +27714,7 @@
            [(match_operand:V4SF 1 "register_operand" "0")
             (match_operand:V64SF 2 "register_operand" "v")
             (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD)
-         (match_operand:V4SF 4 "const0_operand" "C")
+         (match_operand:V4SF 4 "const0_operand")
          (match_operand:QI 5 "register_operand" "Yk")))]
   "TARGET_AVX5124FMAPS"
   "v4fmaddss\t{%3, %x2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %x2, %3}"
@@ -27755,7 +27755,7 @@
            [(match_operand:V16SF 1 "register_operand" "0")
             (match_operand:V64SF 2 "register_operand" "v")
             (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD)
-         (match_operand:V16SF 4 "const0_operand" "C")
+         (match_operand:V16SF 4 "const0_operand")
          (match_operand:HI 5 "register_operand" "Yk")))]
   "TARGET_AVX5124FMAPS"
   "v4fnmaddps\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
@@ -27796,7 +27796,7 @@
            [(match_operand:V4SF 1 "register_operand" "0")
             (match_operand:V64SF 2 "register_operand" "v")
             (match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD)
-         (match_operand:V4SF 4 "const0_operand" "C")
+         (match_operand:V4SF 4 "const0_operand")
          (match_operand:QI 5 "register_operand" "Yk")))]
   "TARGET_AVX5124FMAPS"
   "v4fnmaddss\t{%3, %x2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %x2, %3}"
@@ -27837,7 +27837,7 @@
            [(match_operand:V16SI 1 "register_operand" "0")
             (match_operand:V64SI 2 "register_operand" "v")
             (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSD)
-         (match_operand:V16SI 4 "const0_operand" "C")
+         (match_operand:V16SI 4 "const0_operand")
          (match_operand:HI 5 "register_operand" "Yk")))]
   "TARGET_AVX5124VNNIW"
   "vp4dpwssd\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
@@ -27878,7 +27878,7 @@
            [(match_operand:V16SI 1 "register_operand" "0")
             (match_operand:V64SI 2 "register_operand" "v")
             (match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSDS)
-         (match_operand:V16SI 4 "const0_operand" "C")
+         (match_operand:V16SI 4 "const0_operand")
          (match_operand:HI 5 "register_operand" "Yk")))]
   "TARGET_AVX5124VNNIW"
   "vp4dpwssds\t{%3, %g2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %g2, %3}"
@@ -27954,7 +27954,7 @@
        (unspec:VI1_AVX512F
          [(match_operand:VI1_AVX512F 1 "register_operand" "0,v")
           (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm")
-          (match_operand 3 "const_0_to_255_operand" "n,n")]
+          (match_operand 3 "const_0_to_255_operand")]
          UNSPEC_GF2P8AFFINEINV))]
   "TARGET_GFNI"
   "@
@@ -27971,7 +27971,7 @@
        (unspec:VI1_AVX512F
          [(match_operand:VI1_AVX512F 1 "register_operand" "0,v")
           (match_operand:VI1_AVX512F 2 "vector_operand" "xBm,vm")
-          (match_operand 3 "const_0_to_255_operand" "n,n")]
+          (match_operand 3 "const_0_to_255_operand")]
          UNSPEC_GF2P8AFFINE))]
   "TARGET_GFNI"
   "@
@@ -28004,7 +28004,7 @@
        (unspec:VI248_AVX512VL
          [(match_operand:VI248_AVX512VL 1 "register_operand" "v")
           (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm")
-          (match_operand:SI 3 "const_0_to_255_operand" "n")]
+          (match_operand:SI 3 "const_0_to_255_operand")]
          UNSPEC_VPSHRD))]
   "TARGET_AVX512VBMI2"
   "vpshrd<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3 }"
@@ -28015,7 +28015,7 @@
        (unspec:VI248_AVX512VL
          [(match_operand:VI248_AVX512VL 1 "register_operand" "v")
           (match_operand:VI248_AVX512VL 2 "nonimmediate_operand" "vm")
-          (match_operand:SI 3 "const_0_to_255_operand" "n")]
+          (match_operand:SI 3 "const_0_to_255_operand")]
          UNSPEC_VPSHLD))]
   "TARGET_AVX512VBMI2"
   "vpshld<ssemodesuffix>\t{%3, %2, %1, %0<mask_operand4>|%0<mask_operand4>, %1, %2, %3 }"
@@ -28071,7 +28071,7 @@
             (match_operand:VI248_AVX512VL 2 "register_operand" "v")
             (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
            UNSPEC_VPSHRDV)
-         (match_operand:VI248_AVX512VL 4 "const0_operand" "C")
+         (match_operand:VI248_AVX512VL 4 "const0_operand")
          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VBMI2"
   "vpshrdv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
@@ -28128,7 +28128,7 @@
             (match_operand:VI248_AVX512VL 2 "register_operand" "v")
             (match_operand:VI248_AVX512VL 3 "nonimmediate_operand" "vm")]
            UNSPEC_VPSHLDV)
-         (match_operand:VI248_AVX512VL 4 "const0_operand" "C")
+         (match_operand:VI248_AVX512VL 4 "const0_operand")
          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VBMI2"
   "vpshldv<ssemodesuffix>\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
@@ -28224,7 +28224,7 @@
             (match_operand:VI4_AVX512VL 2 "register_operand" "v")
             (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")
            ] UNSPEC_VPMADDUBSWACCD)
-         (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
+         (match_operand:VI4_AVX512VL 4 "const0_operand")
          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpbusd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
@@ -28292,7 +28292,7 @@
             (match_operand:VI4_AVX512VL 2 "register_operand" "v")
             (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
            UNSPEC_VPMADDUBSWACCSSD)
-         (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
+         (match_operand:VI4_AVX512VL 4 "const0_operand")
          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpbusds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
@@ -28360,7 +28360,7 @@
             (match_operand:VI4_AVX512VL 2 "register_operand" "v")
             (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
            UNSPEC_VPMADDWDACCD)
-         (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
+         (match_operand:VI4_AVX512VL 4 "const0_operand")
          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpwssd\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
@@ -28428,7 +28428,7 @@
             (match_operand:VI4_AVX512VL 2 "register_operand" "v")
             (match_operand:VI4_AVX512VL 3 "nonimmediate_operand" "vm")]
            UNSPEC_VPMADDWDACCSSD)
-         (match_operand:VI4_AVX512VL 4 "const0_operand" "C")
+         (match_operand:VI4_AVX512VL 4 "const0_operand")
          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
   "TARGET_AVX512VNNI"
   "vpdpwssds\t{%3, %2, %0%{%5%}%{z%}|%0%{%5%}%{z%}, %2, %3 }"
@@ -28478,7 +28478,7 @@
   [(set (match_operand:VI8_FVL 0 "register_operand" "=v")
        (unspec:VI8_FVL [(match_operand:VI8_FVL 1 "register_operand" "v")
                         (match_operand:VI8_FVL 2 "vector_operand" "vm")
-                        (match_operand:SI 3 "const_0_to_255_operand" "n")]
+                        (match_operand:SI 3 "const_0_to_255_operand")]
                        UNSPEC_VPCLMULQDQ))]
   "TARGET_VPCLMULQDQ"
   "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"

diff --git a/gcc/config/i386/subst.md b/gcc/config/i386/subst.md
index bb86f82..0b75882 100644 (file)
--- a/gcc/config/i386/subst.md
+++ b/gcc/config/i386/subst.md
@@ -137,7 +137,7 @@
  [(set (match_dup 0)
        (vec_merge:SUBST_V
         (match_dup 1)
-        (match_operand:SUBST_V 2 "const0_operand" "C")
+        (match_operand:SUBST_V 2 "const0_operand")
         (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")))
 ])
 
@@ -155,7 +155,7 @@
        (vec_merge:SUBST_V
          (vec_merge:SUBST_V
            (match_dup 1)
-           (match_operand:SUBST_V 3 "const0_operand" "C")
+           (match_operand:SUBST_V 3 "const0_operand")
            (match_operand:<avx512fmaskmode> 4 "register_operand" "Yk"))
          (match_dup 2)
          (const_int 1)))])
@@ -171,7 +171,7 @@
  [(set (match_dup 0)
        (vec_merge:SUBST_CV
         (match_dup 1)
-        (match_operand:SUBST_CV 2 "const0_operand" "C")
+        (match_operand:SUBST_CV 2 "const0_operand")
         (unspec:<avx512fmaskmode>
           [(match_operand:<avx512fmaskcmode> 3 "register_operand" "Yk")]
           UNSPEC_COMPLEX_MASK)))
@@ -372,7 +372,7 @@
        (vec_merge:SUBST_CV
          (vec_merge:SUBST_CV
            (match_dup 1)
-           (match_operand:SUBST_CV 3 "const0_operand" "C")
+           (match_operand:SUBST_CV 3 "const0_operand")
            (unspec:<avx512fmaskmode>
              [(match_operand:<avx512fmaskcmode> 4 "register_operand" "Yk")]
              UNSPEC_COMPLEX_MASK))
@@ -478,5 +478,5 @@
   [(set (match_dup 0)
         (vec_merge:SUBST_V
          (match_dup 1)
-         (match_operand:SUBST_V 2 "const0_operand" "C")
+         (match_operand:SUBST_V 2 "const0_operand")
          (match_operand:<avx512fmaskhalfmode> 3 "register_operand" "Yk")))])

diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md
index 820e9ca..92634d5 100644 (file)
--- a/gcc/config/i386/sync.md
+++ b/gcc/config/i386/sync.md
@@ -745,10 +745,10 @@
            [(match_operand:SWI 0 "memory_operand" "+m")
             (match_operand:SI 3 "const_int_operand")]          ;; model
            UNSPECV_XCHG)
-         (match_operand:SWI 2 "const_int_operand" "i")))
+         (match_operand:SWI 2 "const_int_operand")))
    (set (match_dup 0)
        (plus:SWI (match_dup 0)
-                 (match_operand:SWI 1 "const_int_operand" "i")))]
+                 (match_operand:SWI 1 "const_int_operand")))]
   "(unsigned HOST_WIDE_INT) INTVAL (operands[1])
    == -(unsigned HOST_WIDE_INT) INTVAL (operands[2])"
 {

diff --git a/gcc/testsuite/gcc.target/i386/pr105624.c b/gcc/testsuite/gcc.target/i386/pr105624.c
index 8ca6c43..aa5895b 100644 (file)
--- a/gcc/testsuite/gcc.target/i386/pr105624.c
+++ b/gcc/testsuite/gcc.target/i386/pr105624.c
@@ -1,5 +1,5 @@
 /* PR target/105624 */
-/* { dg-do compile } */
+/* { dg-do compile { target { ! ia32 } } } */
 /* { dg-options "-O1 -march=k8" } */
 
 union U {