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drm/amdgpu: update GC golden setting for dimgrey_cavefish
author
Tao Zhou
<tao.zhou1@amd.com>
Fri, 27 Nov 2020 03:55:30 +0000
(11:55 +0800)
committer
Alex Deucher
<alexander.deucher@amd.com>
Tue, 1 Dec 2020 20:59:02 +0000
(15:59 -0500)
Update GC golden setting for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
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diff --git
a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index
841d39e
..
ffbda66
100644
(file)
--- a/
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@
-3266,6
+3266,7
@@
static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
{
+ SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),