[S5PC100] delete unneeded macro

diff --git a/cpu/arm_cortexa8/s5pc100/interrupts.c b/cpu/arm_cortexa8/s5pc100/interrupts.c
index a0175cc..9d28bf9 100644 (file)
--- a/cpu/arm_cortexa8/s5pc100/interrupts.c
+++ b/cpu/arm_cortexa8/s5pc100/interrupts.c
@@ -70,14 +70,14 @@ int interrupt_init(void)
 
        /* use PWM Timer 4 because it has no ouput */
        /* prescaler for timer 4 is 16 */
-       timers->TCFG0 = TCFG0_PRE1(16-1);
+       timers->TCFG0 = ((16-1) & 0xff) << 8;
        if (timer_load_val == 0) {
                /*
                 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
                 * (default) and prescaler = 16. Should be 20859
                 * @66.75MHz
                 */
-               timers->TCFG1 = TCFG1_MUX4(2-1);
+               timers->TCFG1 = ((2-1) & 0xf) << 16;
                timer_load_val = get_PCLK() / (2 * 16 * 100);
        }
 

diff --git a/include/s5pc1xx.h b/include/s5pc1xx.h
index b0c621e..7c62719 100644 (file)
--- a/include/s5pc1xx.h
+++ b/include/s5pc1xx.h
@@ -6,7 +6,7 @@
 #ifndef __S5PC100_H__
 #define __S5PC100_H__
 
-#include <asm/hardware.h>
+#define __REG(x)       (*(vu_long *)(x))
 
 #define S5P_ADDR_BASE  (0xe0000000)
 #define S5P_ADDR(x)            (S5P_ADDR_BASE + (x))
@@ -1399,6 +1399,7 @@
 /* PWM */
 #define S5P_PWMTIMER_BASE(x)   (S5P_PA_PWMTIMER + (x))
 
+/* PWM timer offset */
 #define PWM_TCFG0_OFFSET               0x0
 #define PWM_TCFG1_OFFSET               0x04
 #define PWM_TCON_OFFSET                        0x08
@@ -1417,6 +1418,7 @@
 #define PWM_TCNTO4_OFFSET              0x40
 #define PWM_TINT_CSTAT_OFFSET  0x44
 
+/* PWM timer register */
 #define S5P_PWM_TCFG0          S5P_PWMTIMER_BASE(PWM_TCFG0_OFFSET)
 #define S5P_PWM_TCFG1          S5P_PWMTIMER_BASE(PWM_TCFG1_OFFSET)
 #define S5P_PWM_TCON           S5P_PWMTIMER_BASE(PWM_TCON_OFFSET)
@@ -1435,6 +1437,7 @@
 #define S5P_PWM_TCNTO4         S5P_PWMTIMER_BASE(PWM_TCNTO4_OFFSET)
 #define S5P_PWM_TINT_CSTAT     S5P_PWMTIMER_BASE(PWM_TINT_CSTAT_OFFSET)
 
+/* PWM timer addressing */
 #define S5P_TIMER_BASE                 S5P_PWMTIMER_BASE(0x0)
 #define S5P_PWMTIMER_BASE_REG  __REG(S5P_PWMTIMER_BASE(0x0))
 #define S5P_PWM_TCFG0_REG              __REG(S5P_PWM_TCFG0)
@@ -1455,6 +1458,14 @@
 #define S5P_PWM_TCNTO4_REG             __REG(S5P_PWM_TCNTO4_REG)
 #define S5P_PWM_TINT_CSTAT_REG __REG(S5P_PWM_TINT_CSTAT)
 
+/* PWM timer value */
+#define TCON_4_AUTO            (1 << 22)  /* auto reload on/off for Timer 4 */
+#define TCON_4_UPDATE          (1 << 21)  /* manual Update TCNTB4 */
+#define TCON_4_ONOFF           (1 << 20)  /* 0: Stop, 1: start Timer 4 */
+#define COUNT_4_ON             (TCON_4_ONOFF * 1)
+#define COUNT_4_OFF            (TCON_4_ONOFF * 0)
+
+
 
 /* System Timer */
 #define S5P_SYSTIMER_BASE(x)   (S5P_PA_SYSTEM + (x))
@@ -1569,94 +1580,6 @@
 #define UTRSTAT_RX_READY       (1 << 0)
 #define UART_ERR_MASK          0xF
 
-
-
-/*
- *
- */
-
-/* fields */
-#define fTCFG0_DZONE           Fld(8, 16) /* the dead zone length (=timer 0) */
-#define fTCFG0_PRE1            Fld(8, 8)  /* prescaler value for time 2,3,4 */
-#define fTCFG0_PRE0            Fld(8, 0)  /* prescaler value for time 0,1 */
-#define fTCFG1_MUX4            Fld(4, 16)
-
-/* bits */
-#define TCFG0_DZONE(x)         FInsrt((x), fTCFG0_DZONE)
-#define TCFG0_PRE1(x)          FInsrt((x), fTCFG0_PRE1)
-#define TCFG0_PRE0(x)          FInsrt((x), fTCFG0_PRE0)
-#define TCFG1_MUX4(x)          FInsrt((x), fTCFG1_MUX4)
-
-#define TCON_4_AUTO            (1 << 22)  /* auto reload on/off for Timer 4 */
-#define TCON_4_UPDATE          (1 << 21)  /* manual Update TCNTB4 */
-#define TCON_4_ONOFF           (1 << 20)  /* 0: Stop, 1: start Timer 4 */
-#define COUNT_4_ON             (TCON_4_ONOFF * 1)
-#define COUNT_4_OFF            (TCON_4_ONOFF * 0)
-#define TCON_3_AUTO            (1 << 19)  /* auto reload on/off for Timer 3 */
-#define TIMER3_ATLOAD_ON       (TCON_3_AUTO * 1)
-#define TIMER3_ATLAOD_OFF      FClrBit(TCON, TCON_3_AUTO)
-#define TCON_3_INVERT          (1 << 18)  /* 1: Inverter on for TOUT3 */
-#define TIMER3_IVT_ON          (TCON_3_INVERT * 1)
-#define TIMER3_IVT_OFF         (FClrBit(TCON, TCON_3_INVERT))
-#define TCON_3_MAN             (1 << 17)  /* manual Update TCNTB3,TCMPB3 */
-#define TIMER3_MANUP           (TCON_3_MAN*1)
-#define TIMER3_NOP             (FClrBit(TCON, TCON_3_MAN))
-#define TCON_3_ONOFF           (1 << 16)  /* 0: Stop, 1: start Timer 3 */
-#define TIMER3_ON              (TCON_3_ONOFF * 1)
-#define TIMER3_OFF             (FClrBit(TCON, TCON_3_ONOFF))
-
-#if defined(CONFIG_CLK_400_100_50)
-#define STARTUP_AMDIV          400
-#define STARTUP_MDIV           400
-#define STARTUP_PDIV           6
-#define STARTUP_SDIV           1
-#elif defined(CONFIG_CLK_400_133_66)
-#define STARTUP_AMDIV          400
-#define STARTUP_MDIV           533
-#define STARTUP_PDIV           6
-#define STARTUP_SDIV           1
-#elif defined(CONFIG_CLK_533_133_66)
-#define STARTUP_AMDIV          533
-#define STARTUP_MDIV           533
-#define STARTUP_PDIV           6
-#define STARTUP_SDIV           1
-#elif defined(CONFIG_CLK_667_133_66)
-#define STARTUP_AMDIV          667
-#define STARTUP_MDIV           533
-#define STARTUP_PDIV           6
-#define STARTUP_SDIV           1
-#endif
-
-#define        STARTUP_PCLKDIV         3
-#define STARTUP_HCLKX2DIV      1
-#define STARTUP_HCLKDIV                1
-#define STARTUP_MPLLDIV                1
-#define STARTUP_APLLDIV                0
-
-#define CLK_DIV_VAL    ((STARTUP_PCLKDIV << 12) | (STARTUP_HCLKX2DIV << 9) | \
-       (STARTUP_HCLKDIV << 8) | (STARTUP_MPLLDIV<<4) | STARTUP_APLLDIV)
-#define MPLL_VAL       ((1 << 31) | (STARTUP_MDIV << 16) | \
-       (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_MPLL   (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
-       STARTUP_PDIV) * STARTUP_MDIV)
-
-#if defined(CONFIG_SYNC_MODE)
-#define APLL_VAL       ((1 << 31) | (STARTUP_MDIV << 16) | \
-       (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL   (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
-       STARTUP_PDIV) * STARTUP_MDIV)
-#define STARTUP_HCLK   (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
-       (STARTUP_HCLKDIV + 1))
-#else
-#define APLL_VAL       ((1 << 31) | (STARTUP_AMDIV << 16) | \
-       (STARTUP_PDIV << 8) | STARTUP_SDIV)
-#define STARTUP_APLL   (((CONFIG_SYS_CLK_FREQ >> STARTUP_SDIV) / \
-       STARTUP_PDIV) * STARTUP_AMDIV)
-#define STARTUP_HCLK   (STARTUP_MPLL / (STARTUP_HCLKX2DIV + 1) / \
-       (STARTUP_HCLKDIV + 1))
-#endif
-
-
 #ifndef __ASSEMBLY__
 enum s5pc1xx_uarts_nr {
        S5PC1XX_UART0,