config GENERIC_CLOCKEVENTS
def_bool n
+config SYS_SUPPORTS_PM
+ bool
+
config SYS_SUPPORTS_APM_EMULATION
bool
+ select SYS_SUPPORTS_PM
+
+config SYS_SUPPORTS_SMP
+ bool
+
+config SYS_SUPPORTS_NUMA
+ bool
+
+config SYS_SUPPORTS_PCI
+ bool
config ARCH_MAY_HAVE_PC_FDC
bool
config SH_FPU
bool "FPU support"
- depends on !CPU_SH3
+ depends on CPU_SH4
default y
help
Selecting this option will enable support for SH processors that
config SH_7780_SOLUTION_ENGINE
bool "SolutionEngine7780"
select SOLUTION_ENGINE
+ select SYS_SUPPORTS_PCI
depends on CPU_SUBTYPE_SH7780
help
Select 7780 SolutionEngine if configuring for a Renesas SH7780
config SH_HP6XX
bool "HP6XX"
select SYS_SUPPORTS_APM_EMULATION
+ select HD6446X_SERIES
depends on CPU_SUBTYPE_SH7709
help
Select HP6XX if configuring for a HP jornada HP6xx.
More information (hardware only) at
<http://www.hp.com/jornada/>.
-config SH_SATURN
- bool "Saturn"
- depends on CPU_SUBTYPE_SH7604
- help
- Select Saturn if configuring for a SEGA Saturn.
-
config SH_DREAMCAST
bool "Dreamcast"
+ select SYS_SUPPORTS_PCI
depends on CPU_SUBTYPE_SH7091
help
Select Dreamcast if configuring for a SEGA Dreamcast.
config SH_SH03
bool "Interface CTP/PCI-SH03"
depends on CPU_SUBTYPE_SH7751 && BROKEN
+ select SYS_SUPPORTS_PCI
help
CTP/PCI-SH03 is a CPU module computer that is produced
by Interface Corporation.
config SH_SECUREEDGE5410
bool "SecureEdge5410"
depends on CPU_SUBTYPE_SH7751R
+ select SYS_SUPPORTS_PCI
help
Select SecureEdge5410 if configuring for a SnapGear SH board.
This includes both the OEM SecureEdge products as well as the
config SH_RTS7751R2D
bool "RTS7751R2D"
depends on CPU_SUBTYPE_SH7751R
+ select SYS_SUPPORTS_PCI
help
Select RTS7751R2D if configuring for a Renesas Technology
Sales SH-Graphics board.
config SH_HIGHLANDER
bool "Highlander"
depends on CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785
+ select SYS_SUPPORTS_PCI
config SH_EDOSK7705
bool "EDOSK7705"
config SH_LANDISK
bool "LANDISK"
depends on CPU_SUBTYPE_SH7751R
+ select SYS_SUPPORTS_PCI
help
I-O DATA DEVICE, INC. "LANDISK Series" support.
config SH_TITAN
bool "TITAN"
depends on CPU_SUBTYPE_SH7751R
+ select SYS_SUPPORTS_PCI
help
Select Titan if you are configuring for a Nimble Microsystems
NetEngine NP51R.
config SH_LBOX_RE2
bool "L-BOX RE2"
depends on CPU_SUBTYPE_SH7751R
+ select SYS_SUPPORTS_PCI
help
Select L-BOX RE2 if configuring for the NTT COMWARE L-BOX RE2.
config SH_CLK_MD
int "CPU Mode Pin Setting"
- default 0
depends on CPU_SUBTYPE_SH7619 || CPU_SUBTYPE_SH7206
+ default 6 if CPU_SUBTYPE_SH7206
+ default 5 if CPU_SUBTYPE_SH7619
+ default 0
help
MD2 - MD0 pin setting.
config SMP
bool "Symmetric multi-processing support"
+ depends on SYS_SUPPORTS_SMP
---help---
This enables support for systems with more than one CPU. If you have
a system with only one CPU, like most personal computers, say N. If
config UBC_WAKEUP
bool "Wakeup UBC on startup"
+ depends on CPU_SH4
help
Selecting this option will wakeup the User Break Controller (UBC) on
startup. Although the UBC is left in an awake state when the processor
# we're not using PCMCIA, so we make it dependent on
# PCMCIA outright. -- PFM.
config ISA
- bool
- default y if PCMCIA
+ def_bool y
+ depends on PCMCIA && HD6446X_SERIES
help
Find out whether you have ISA slots on your motherboard. ISA is the
name of a bus system, i.e. the way the CPU talks to the other stuff
endmenu
menu "Power management options (EXPERIMENTAL)"
-depends on EXPERIMENTAL
+depends on EXPERIMENTAL && SYS_SUPPORTS_PM
source kernel/power/Kconfig
bool "Include KGDB kernel debugger"
select FRAME_POINTER
select DEBUG_INFO
+ depends on CPU_SH3 || CPU_SH4
help
Include in-kernel hooks for kgdb, the Linux kernel source level
debugger. See <http://kgdb.sourceforge.net/> for more information.
are additional GPIO bits that can be used to interface to
external as well.
-# A board must have defined HD6446X_SERIES in order to see these
config HD6446X_SERIES
- bool "HD6446x support"
- default n
+ bool
choice
prompt "HD6446x options"
config HD64461
bool "Hitachi HD64461 companion chip support"
- depends on CPU_SUBTYPE_SH7709
---help---
The Hitachi HD64461 provides an interface for
the SH7709 CPU, supporting a LCD controller,
config HD64465
bool "Hitachi HD64465 companion chip support"
- depends on CPU_SUBTYPE_SH7750
---help---
The Hitachi HD64465 provides an interface for
the SH7750 CPU, supporting a LCD controller,
config PCI
bool "PCI support"
+ depends on SYS_SUPPORTS_PCI
help
Find out whether you have a PCI motherboard. PCI is the name of a
bus system, i.e. the way the CPU talks to the other stuff inside
#include <asm/cacheflush.h>
#include <asm/cache.h>
#include <asm/io.h>
-
-extern void detect_cpu_and_cache_system(void);
+#include <asm/ubc.h>
/*
* Generic wrapper for command line arguments to disable on-chip
flags |= CCR_CACHE_CB;
#endif
-#ifdef CONFIG_SH_OCRAM
- /* Turn on OCRAM -- halve the OC */
- flags |= CCR_CACHE_ORA;
- current_cpu_data.dcache.sets >>= 1;
-
- current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
- current_cpu_data.dcache.linesz;
-#endif
-
ctrl_outl(flags, CCR);
back_to_P1();
}
}
#endif
-#ifdef CONFIG_UBC_WAKEUP
/*
* Some brain-damaged loaders decided it would be a good idea to put
* the UBC to sleep. This causes some issues when it comes to things
* we wake it up and hope that all is well.
*/
ubc_wakeup();
-#endif
-
speculative_execution_init();
}
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
-
-
#include <linux/init.h>
+#include <linux/smp.h>
#include <asm/processor.h>
#include <asm/cache.h>
ctrl_outl(pc, UBC_BARA);
#ifdef CONFIG_MMU
- /* We don't have any ASID settings for the SH-2! */
- if (current_cpu_data.type != CPU_SH7604)
- ctrl_outb(asid, UBC_BASRA);
+ ctrl_outb(asid, UBC_BASRA);
#endif
ctrl_outl(0, UBC_BAMRA);
config CPU_SUBTYPE_SH7619
bool "Support SH7619 processor"
select CPU_SH2
+ select CPU_HAS_IPR_IRQ
# SH-2A Processor Support
select CPU_SHX2
select CPU_HAS_IPR_IRQ
select ARCH_SPARSEMEM_ENABLE
+ select SYS_SUPPORTS_NUMA
endchoice
config NUMA
bool "Non Uniform Memory Access (NUMA) Support"
- depends on MMU && SPARSEMEM && EXPERIMENTAL
+ depends on MMU && SYS_SUPPORTS_NUMA && EXPERIMENTAL
default n
help
Some SH systems have many various memories scattered around
config ARCH_FLATMEM_ENABLE
def_bool y
+ depends on !NUMA
config ARCH_SPARSEMEM_ENABLE
def_bool y
If unsure, say N.
-config SH_OCRAM
- bool "Operand Cache RAM (OCRAM) support"
- help
- Selecting this option will automatically tear down the number of
- sets in the dcache by half, which in turn exposes a memory range.
-
- The addresses for the OC RAM base will vary according to the
- processor version. Consult vendor documentation for specifics.
-
- If unsure, say N.
-
endmenu
}
EXPORT_SYMBOL_GPL(remove_memory);
+#ifdef CONFIG_NUMA
int memory_add_physaddr_to_nid(u64 addr)
{
/* Node 0 for now.. */
}
EXPORT_SYMBOL_GPL(memory_add_physaddr_to_nid);
#endif
+#endif
#define __ASM_SH_CACHE_H
#ifdef __KERNEL__
+#include <linux/init.h>
#include <asm/cpu/cache.h>
#define SH_CACHE_VALID 1
unsigned long flags;
};
+
+int __init detect_cpu_and_cache_system(void);
+
#endif /* __ASSEMBLY__ */
#endif /* __KERNEL__ */
#endif /* __ASM_SH_CACHE_H */
#define HD64461_NIRR 0x15000
#define HD64461_NIMR 0x15002
-#define HD64461_IRQBASE OFFCHIP_IRQ_BASE
+#define HD64461_IRQBASE 64
#define HD64461_IRQ_NUM 16
#define HD64461_IRQ_UART (HD64461_IRQBASE+5)
regs->sr &= ~SR_FD;
}
-#ifdef CONFIG_CPU_SH4
extern void save_fpu(struct task_struct *__tsk, struct pt_regs *regs);
-#else
-#define save_fpu(tsk) do { } while (0)
-#endif
#define unlazy_fpu(tsk, regs) do { \
if (test_tsk_thread_flag(tsk, TIF_USEDFPU)) { \
#define smp_read_barrier_depends() do { } while(0)
#endif
-#define set_mb(var, value) do { xchg(&var, value); } while (0)
+#define set_mb(var, value) do { (void)xchg(&var, value); } while (0)
/*
* Jump to P2 area.
#define BRCR_UBDE (1 << 0)
#ifndef __ASSEMBLY__
-/* arch/sh/kernel/ubc.S */
-extern void ubc_wakeup(void);
+/* arch/sh/kernel/cpu/ubc.S */
extern void ubc_sleep(void);
+
+#ifdef CONFIG_UBC_WAKEUP
+extern void ubc_wakeup(void);
+#else
+#define ubc_wakeup() do { } while (0)
+#endif
#endif
#endif /* __KERNEL__ */