class HWInstructionIssuedEvent : public HWInstructionEvent {
public:
using ResourceRef = std::pair<uint64_t, uint64_t>;
- HWInstructionIssuedEvent(
- unsigned Index, llvm::ArrayRef<std::pair<ResourceRef, unsigned>> UR)
+ HWInstructionIssuedEvent(unsigned Index,
+ llvm::ArrayRef<std::pair<ResourceRef, unsigned>> UR)
: HWInstructionEvent(HWInstructionEvent::Issued, Index),
UsedResources(UR) {}
private:
virtual void anchor();
};
-
} // namespace mca
#endif
}
const InstrDesc &InstrBuilder::getOrCreateInstrDesc(const MCInst &MCI) {
- auto it = Descriptors.find(MCI.getOpcode());
- if (it == Descriptors.end())
+ if (Descriptors.find_as(MCI.getOpcode()) == Descriptors.end())
createInstrDescImpl(MCI);
- return *Descriptors[MCI.getOpcode()].get();
+ return *Descriptors[MCI.getOpcode()];
}
std::unique_ptr<Instruction>
for (const WriteDescriptor &WD : D.Writes) {
unsigned RegID =
WD.OpIndex == -1 ? WD.RegisterID : MCI.getOperand(WD.OpIndex).getReg();
- assert((RegID || WD.IsOptionalDef) && "Expected a valid register ID!");
- // Special case where this is a optional definition, and the actual register
- // is 0.
+ // Check if this is a optional definition that references NoReg.
if (WD.IsOptionalDef && !RegID)
continue;
+ assert(RegID && "Expected a valid register ID!");
NewIS->getDefs().emplace_back(llvm::make_unique<WriteState>(WD, RegID));
}
}
#endif
-bool Instruction::isReady() {
- if (Stage == IS_READY)
- return true;
+void Instruction::dispatch() {
+ assert(Stage == IS_INVALID);
+ Stage = IS_AVAILABLE;
- assert(Stage == IS_AVAILABLE);
- for (const UniqueUse &Use : Uses)
- if (!Use.get()->isReady())
- return false;
-
- setReady();
- return true;
+ if (std::all_of(Uses.begin(), Uses.end(),
+ [](const UniqueUse &Use) { return Use->isReady(); }))
+ Stage = IS_READY;
}
void Instruction::execute() {
Stage = IS_EXECUTING;
for (UniqueDef &Def : Defs)
Def->onInstructionIssued();
+ if (!CyclesLeft)
+ Stage = IS_EXECUTED;
}
bool Instruction::isZeroLatency() const {
}
void Instruction::cycleEvent() {
+ if (isReady())
+ return;
+
if (isDispatched()) {
- for (UniqueUse &Use : Uses)
+ bool IsReady = true;
+ for (UniqueUse &Use : Uses) {
Use->cycleEvent();
+ IsReady &= Use->isReady();
+ }
+
+ if (IsReady)
+ Stage = IS_READY;
return;
}
- if (isExecuting()) {
- for (UniqueDef &Def : Defs)
- Def->cycleEvent();
- CyclesLeft--;
- }
+
+ assert(isExecuting() && "Instruction not in-flight?");
+ assert(CyclesLeft && "Instruction already executed?");
+ for (UniqueDef &Def : Defs)
+ Def->cycleEvent();
+ CyclesLeft--;
if (!CyclesLeft)
Stage = IS_EXECUTED;
}
-
} // namespace mca
// One entry per each implicit and explicit register use.
VecUses Uses;
- // This instruction has already been dispatched, and all operands are ready.
- void setReady() {
- assert(Stage == IS_AVAILABLE);
- Stage = IS_READY;
- }
-
public:
Instruction(const InstrDesc &D)
: Desc(D), Stage(IS_INVALID), CyclesLeft(-1) {}
// Transition to the dispatch stage.
// No definition is updated because the instruction is not "executing".
- void dispatch() {
- assert(Stage == IS_INVALID);
- Stage = IS_AVAILABLE;
- }
+ void dispatch();
// Instruction issued. Transition to the IS_EXECUTING state, and update
// all the definitions.
Stage = IS_EXECUTED;
}
- // Checks if operands are available. If all operands area ready,
- // then this forces a transition from IS_AVAILABLE to IS_READY.
- bool isReady();
-
bool isDispatched() const { return Stage == IS_AVAILABLE; }
+ bool isReady() const { return Stage == IS_READY; }
bool isExecuting() const { return Stage == IS_EXECUTING; }
bool isExecuted() const { return Stage == IS_EXECUTED; }
bool isZeroLatency() const;
void retire() {
- assert(Stage == IS_EXECUTED);
+ assert(isExecuted() && "Instruction is in an invalid state!");
Stage = IS_RETIRED;
}
if (ProcResource.SubUnitsIdxBegin || !NumUnits)
continue;
- Resource2VecIndex.insert(std::pair<uint64_t, unsigned>(I, R2VIndex));
+ Resource2VecIndex.insert(std::pair<unsigned, unsigned>(I, R2VIndex));
R2VIndex += ProcResource.NumUnits;
}
OS << " ";
else
OS << " ";
- ResourceIndex++;
- continue;
- }
-
- for (unsigned J = 0; J < NumUnits; ++J) {
- OS << "[" << ResourceIndex << '.' << J << ']';
- if (ResourceIndex < 10)
- OS << " ";
- else
- OS << ' ';
+ } else {
+ for (unsigned J = 0; J < NumUnits; ++J) {
+ OS << "[" << ResourceIndex << '.' << J << ']';
+ if (ResourceIndex < 10)
+ OS << " ";
+ else
+ OS << ' ';
+ }
}
ResourceIndex++;
}
printColumnNames(TempStream, SM);
TempStream << '\n';
- for (unsigned I = 0; I < NumResourceUnits; ++I) {
- unsigned Usage = ResourceUsage[I + Source.size() * NumResourceUnits];
+ for (unsigned I = 0, E = NumResourceUnits; I < E; ++I) {
+ unsigned Usage = ResourceUsage[I + Source.size() * E];
if (!Usage) {
TempStream << " - ";
continue;
#include "SourceMgr.h"
#include "View.h"
+#include "llvm/ADT/DenseMap.h"
#include "llvm/MC/MCInstPrinter.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include <map>
llvm::MCInstPrinter &MCIP;
const SourceMgr &Source;
- // Map to quickly get a resource descriptor from a mask.
- std::map<uint64_t, unsigned> Resource2VecIndex;
+ // Map to quickly obtain the ResourceUsage column index from a processor
+ // resource ID.
+ llvm::DenseMap<unsigned, unsigned> Resource2VecIndex;
// Table of resources used by instructions.
std::vector<unsigned> ResourceUsage;
void initialize();
public:
- ResourcePressureView(const llvm::MCSubtargetInfo &ST,
+ ResourcePressureView(const llvm::MCSubtargetInfo &sti,
llvm::MCInstPrinter &Printer, const SourceMgr &SM)
- : STI(ST), MCIP(Printer), Source(SM) {
+ : STI(sti), MCIP(Printer), Source(SM) {
initialize();
}
// This updates the internal state of each write.
IS.execute();
+ notifyInstructionIssued(InstrIndex, UsedResources);
if (D.MaxLatency) {
+ assert(IS.isExecuting() && "A zero latency instruction?");
IssuedQueue[InstrIndex] = &IS;
- notifyInstructionIssued(InstrIndex, UsedResources);
- } else {
- // A zero latency instruction which reads and/or updates registers.
- notifyInstructionIssued(InstrIndex, UsedResources);
- notifyInstructionExecuted(InstrIndex);
+ return;
}
+
+ // A zero latency instruction which reads and/or updates registers.
+ assert(IS.isExecuted() && "Instruction still executing!");
+ notifyInstructionExecuted(InstrIndex);
}
void Scheduler::issue() {
-//===--------------------- Support.cpp ----------------------------*- C++
-//-*-===//
+//===--------------------- Support.cpp --------------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
-//===--------------------- TimelineView.cpp ---------------*- C++ -*-===//
+//===--------------------- TimelineView.cpp ---------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
-//===--------------------- TimelineView.h ---------------*- C++ -*-===//
+//===--------------------- TimelineView.h -----------------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
const unsigned DEFAULT_ITERATIONS = 10;
+ void initialize(unsigned MaxIterations);
+
public:
TimelineView(const llvm::MCSubtargetInfo &sti, llvm::MCInstPrinter &Printer,
const SourceMgr &Sequence, unsigned MaxIterations,
initialize(MaxIterations);
}
- void initialize(unsigned MaxIterations);
-
// Event handlers.
void onCycleBegin(unsigned Cycle) override { CurrentCycle = Cycle; }
void onInstructionEvent(const HWInstructionEvent &Event) override;
const InstVec &GetInstructionSequence() const { return Insts; }
};
-
} // end of anonymous namespace
int main(int argc, char **argv) {
std::unique_ptr<mca::BackendPrinter> Printer =
llvm::make_unique<mca::BackendPrinter>(*B);
- std::unique_ptr<mca::SummaryView> SV =
- llvm::make_unique<mca::SummaryView>(*STI, *MCII, *S, *IP, Width);
- Printer->addView(std::move(SV));
+ Printer->addView(
+ llvm::make_unique<mca::SummaryView>(*STI, *MCII, *S, *IP, Width));
- if (PrintModeVerbose) {
- std::unique_ptr<mca::BackendStatistics> BS =
- llvm::make_unique<mca::BackendStatistics>(*STI);
- Printer->addView(std::move(BS));
- }
+ if (PrintModeVerbose)
+ Printer->addView(llvm::make_unique<mca::BackendStatistics>(*STI));
- std::unique_ptr<mca::ResourcePressureView> RPV =
- llvm::make_unique<mca::ResourcePressureView>(*STI, *IP, *S);
- Printer->addView(std::move(RPV));
+ Printer->addView(llvm::make_unique<mca::ResourcePressureView>(*STI, *IP, *S));
if (PrintTimelineView) {
- std::unique_ptr<mca::TimelineView> TV =
- llvm::make_unique<mca::TimelineView>(
- *STI, *IP, *S, TimelineMaxIterations, TimelineMaxCycles);
- Printer->addView(std::move(TV));
+ Printer->addView(llvm::make_unique<mca::TimelineView>(
+ *STI, *IP, *S, TimelineMaxIterations, TimelineMaxCycles));
}
B->run();
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