ARM: rmobile: Fix CPGWPR Address define and Settings on Gen3

This patch fixes the write-protect control of CPG.

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>

diff --git a/board/renesas/draak/draak.c b/board/renesas/draak/draak.c
index 852fdda..e7f0bd7 100644 (file)
--- a/board/renesas/draak/draak.c
+++ b/board/renesas/draak/draak.c
@@ -27,7 +27,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define CPGWPCR        0xE6150904
-#define CPGWPR  0xE615090C
+#define CPGWPR  0xE6150900
 
 #define CLK2MHZ(clk)   (clk / 1000 / 1000)
 void s_init(void)
@@ -39,8 +39,8 @@ void s_init(void)
        writel(0xA5A5A500, &rwdt->rwtcsra);
        writel(0xA5A5A500, &swdt->swtcsra);
 
+       writel(0x5A5AFFFF, CPGWPR);
        writel(0xA5A50000, CPGWPCR);
-       writel(0xFFFFFFFF, CPGWPR);
 }
 
 #define GSX_MSTP112            BIT(12) /* 3DG */

diff --git a/board/renesas/salvator-x/salvator-x.c b/board/renesas/salvator-x/salvator-x.c
index 00256bc..746403a 100644 (file)
--- a/board/renesas/salvator-x/salvator-x.c
+++ b/board/renesas/salvator-x/salvator-x.c
@@ -28,7 +28,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define CPGWPCR        0xE6150904
-#define CPGWPR  0xE615090C
+#define CPGWPR  0xE6150900
 
 #define CLK2MHZ(clk)   (clk / 1000 / 1000)
 void s_init(void)
@@ -40,8 +40,8 @@ void s_init(void)
        writel(0xA5A5A500, &rwdt->rwtcsra);
        writel(0xA5A5A500, &swdt->swtcsra);
 
+       writel(0x5A5AFFFF, CPGWPR);
        writel(0xA5A50000, CPGWPCR);
-       writel(0xFFFFFFFF, CPGWPR);
 }
 
 #define GSX_MSTP112            BIT(12) /* 3DG */

diff --git a/board/renesas/ulcb/ulcb.c b/board/renesas/ulcb/ulcb.c
index 213e869..dfe8efd 100644 (file)
--- a/board/renesas/ulcb/ulcb.c
+++ b/board/renesas/ulcb/ulcb.c
@@ -27,7 +27,7 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define CPGWPCR        0xE6150904
-#define CPGWPR  0xE615090C
+#define CPGWPR  0xE6150900
 
 #define CLK2MHZ(clk)   (clk / 1000 / 1000)
 void s_init(void)
@@ -39,8 +39,8 @@ void s_init(void)
        writel(0xA5A5A500, &rwdt->rwtcsra);
        writel(0xA5A5A500, &swdt->swtcsra);
 
+       writel(0x5A5AFFFF, CPGWPR);
        writel(0xA5A50000, CPGWPCR);
-       writel(0xFFFFFFFF, CPGWPR);
 }
 
 #define GSX_MSTP112            BIT(12) /* 3DG */