intel/fs: fix depth compute state for unchanged depth layout
authorLionel Landwerlin <lionel.g.landwerlin@intel.com>
Mon, 8 Jan 2024 10:17:54 +0000 (12:17 +0200)
committerEric Engestrom <eric@engestrom.ch>
Tue, 9 Jan 2024 19:37:45 +0000 (19:37 +0000)
There is no VK CTS exercising this case. If there was we would run
into hangs as noticed in
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26876

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26923>
(cherry picked from commit 4b30b46ffdbc962f09ef87529a71d78cf514f8d8)

.pick_status.json
src/intel/compiler/brw_fs.cpp

index 334507ad35ea6ff0136965444da835102699da8a..6d91a8b0d1f7a461be9a0d080fd4e7874cbd1dab 100644 (file)
         "description": "intel/fs: fix depth compute state for unchanged depth layout",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null,
         "notes": null
index aa01a2241ce029f36edac8b6433eb73d161cfd15..e6a603a9048ba65d19d502c1f28f61998fc418f2 100644 (file)
@@ -7599,7 +7599,17 @@ computed_depth_mode(const nir_shader *shader)
       case FRAG_DEPTH_LAYOUT_LESS:
          return BRW_PSCDEPTH_ON_LE;
       case FRAG_DEPTH_LAYOUT_UNCHANGED:
-         return BRW_PSCDEPTH_OFF;
+         /* We initially set this to OFF, but having the shader write the
+          * depth means we allocate register space in the SEND message. The
+          * difference between the SEND register count and the OFF state
+          * programming makes the HW hang.
+          *
+          * Removing the depth writes also leads to test failures. So use
+          * LesserThanOrEqual, which fits writing the same value
+          * (unchanged/equal).
+          *
+          */
+         return BRW_PSCDEPTH_ON_LE;
       }
    }
    return BRW_PSCDEPTH_OFF;