if (SimplifyDemandedBits(RHS, DemandedMask, OriginalDemandedElts, KnownOp,
TLO, Depth + 1))
return true;
+
+ // Aggressively peek through ops to get at the demanded low bits.
+ SDValue DemandedLHS = SimplifyMultipleUseDemandedBits(
+ LHS, DemandedMask, OriginalDemandedElts, TLO.DAG, Depth + 1);
+ SDValue DemandedRHS = SimplifyMultipleUseDemandedBits(
+ RHS, DemandedMask, OriginalDemandedElts, TLO.DAG, Depth + 1);
+ if (DemandedLHS || DemandedRHS) {
+ DemandedLHS = DemandedLHS ? DemandedLHS : LHS;
+ DemandedRHS = DemandedRHS ? DemandedRHS : RHS;
+ return TLO.CombineTo(
+ Op, TLO.DAG.getNode(Opc, SDLoc(Op), VT, DemandedLHS, DemandedRHS));
+ }
break;
}
case X86ISD::VSHLI: {
if (ISD::isBuildVectorAllZeros(RHS.getNode()))
return RHS;
- // Aggressively peek through ops to get at the demanded low bits.
- APInt DemandedMask = APInt::getLowBitsSet(64, 32);
- SDValue DemandedLHS = DAG.GetDemandedBits(LHS, DemandedMask);
- SDValue DemandedRHS = DAG.GetDemandedBits(RHS, DemandedMask);
- if (DemandedLHS || DemandedRHS)
- return DAG.getNode(N->getOpcode(), SDLoc(N), N->getValueType(0),
- DemandedLHS ? DemandedLHS : LHS,
- DemandedRHS ? DemandedRHS : RHS);
-
// PMULDQ/PMULUDQ only uses lower 32 bits from each vector element.
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
if (TLI.SimplifyDemandedBits(SDValue(N, 0), APInt::getAllOnesValue(64), DCI))