bfd/

	* archures.c (bfd_mach_mips_loongson_2e): New.
	(bfd_mach_mips_loongson_2f): New.
	* bfd-in2.h (bfd_mach_mips_loongson_2e): New.
	(bfd_mach_mips_loongson_2f): New.
	* cpu-mips.c: Add I_loongson_2e and I_loongson_2f to
	anonymous enum.
	(arch_info_struct): Add Loongson-2E and Loongson-2F entries.
	* elfxx-mips.c (_bfd_elf_mips_mach): Handle Loongson-2E
	and Loongson-2F flags.
	(mips_set_isa_flags): Likewise.
	(mips_mach_extensions): Add Loongson-2E and Loongson-2F
	entries.

	binutils/
	* readelf.c (get_machine_flags): Handle Loongson-2E and -2F
	flags.

	gas/
	* config/tc-mips.c (mips_cpu_info_table): Add loongson2e
	and loongson2f entries.
	* doc/c-mips.texi: Document -march=loongson{2e,2f} options.

	gas/testsuite/
	* gas/mips/mips.exp: Add loongson-2e and -2f tests.
	* gas/mips/loongson-2e.d: New.
	* gas/mips/loongson-2e.s: New.
	* gas/mips/loongson-2f.d: New.
	* gas/mips/loongson-2f.s: New.

	include/elf/
	* mips.h (E_MIPS_MACH_LS2E): New.
	(E_MIPS_MACH_LS2F): New.

	include/opcode/
	* mips.h (INSN_LOONGSON_2E): New.
	(INSN_LOONGSON_2F): New.
	(CPU_LOONGSON_2E): New.
	(CPU_LOONGSON_2F): New.
	(OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.

	opcodes/
	* mips-dis.c (mips_arch_choices): Add Loongson-2E and -2F
	entries.
	* mips-opc.c (IL2E): New.
	(IL2F): New.
	(mips_builtin_opcodes): Add Loongson-2E and -2F instructions.
	Allow movz and movn for Loongson-2E and -2F.  Add movnz entry.
	Move coprocessor encodings to the end of the table.  Allow
	certain MIPS V .ps instructions on the Loongson-2E and -2F.

diff --git a/bfd/ChangeLog b/bfd/ChangeLog
index df02dfb..87fc635 100644 (file)
--- a/bfd/ChangeLog
+++ b/bfd/ChangeLog
@@ -1,3 +1,18 @@
+2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
+
+       * archures.c (bfd_mach_mips_loongson_2e): New.
+       (bfd_mach_mips_loongson_2f): New.
+       * bfd-in2.h (bfd_mach_mips_loongson_2e): New.
+       (bfd_mach_mips_loongson_2f): New.
+       * cpu-mips.c: Add I_loongson_2e and I_loongson_2f to
+       anonymous enum.
+       (arch_info_struct): Add Loongson-2E and Loongson-2F entries.
+       * elfxx-mips.c (_bfd_elf_mips_mach): Handle Loongson-2E
+       and Loongson-2F flags.
+       (mips_set_isa_flags): Likewise.
+       (mips_mach_extensions): Add Loongson-2E and Loongson-2F
+       entries. 
+
 2007-11-29  Nick Clifton  <nickc@redhat.com>
 
        PR ld/5398

diff --git a/bfd/archures.c b/bfd/archures.c
index 8f19b7e..3459e55 100644 (file)
--- a/bfd/archures.c
+++ b/bfd/archures.c
@@ -169,6 +169,8 @@ DESCRIPTION
 .#define bfd_mach_mips12000            12000
 .#define bfd_mach_mips16               16
 .#define bfd_mach_mips5                 5
+.#define bfd_mach_mips_loongson_2e      3001
+.#define bfd_mach_mips_loongson_2f      3002
 .#define bfd_mach_mips_sb1              12310201 {* octal 'SB', 01 *}
 .#define bfd_mach_mipsisa32             32
 .#define bfd_mach_mipsisa32r2           33

diff --git a/bfd/bfd-in2.h b/bfd/bfd-in2.h
index 842a536..5de4c90 100644 (file)
--- a/bfd/bfd-in2.h
+++ b/bfd/bfd-in2.h
@@ -1843,6 +1843,8 @@ enum bfd_architecture
 #define bfd_mach_mips12000             12000
 #define bfd_mach_mips16                16
 #define bfd_mach_mips5                 5
+#define bfd_mach_mips_loongson_2e      3001
+#define bfd_mach_mips_loongson_2f      3002
 #define bfd_mach_mips_sb1              12310201 /* octal 'SB', 01 */
 #define bfd_mach_mipsisa32             32
 #define bfd_mach_mipsisa32r2           33

diff --git a/bfd/cpu-mips.c b/bfd/cpu-mips.c
index dbd620a..6384162 100644 (file)
--- a/bfd/cpu-mips.c
+++ b/bfd/cpu-mips.c
@@ -87,6 +87,8 @@ enum
   I_mipsisa64,
   I_mipsisa64r2,
   I_sb1,
+  I_loongson_2e,
+  I_loongson_2f
 };
 
 #define NN(index) (&arch_info_struct[(index) + 1])
@@ -119,7 +121,9 @@ static const bfd_arch_info_type arch_info_struct[] =
   N (32, 32, bfd_mach_mipsisa32r2,"mips:isa32r2", FALSE, NN(I_mipsisa32r2)),
   N (64, 64, bfd_mach_mipsisa64,  "mips:isa64",   FALSE, NN(I_mipsisa64)),
   N (64, 64, bfd_mach_mipsisa64r2,"mips:isa64r2", FALSE, NN(I_mipsisa64r2)),
-  N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, 0),
+  N (64, 64, bfd_mach_mips_sb1, "mips:sb1",       FALSE, NN(I_sb1)),
+  N (64, 64, bfd_mach_mips_loongson_2e, "mips:loongson_2e",       FALSE, NN(I_loongson_2e)),
+  N (64, 64, bfd_mach_mips_loongson_2f, "mips:loongson_2f",       FALSE, 0)
 };
 
 /* The default architecture is mips:3000, but with a machine number of

diff --git a/bfd/elfxx-mips.c b/bfd/elfxx-mips.c
index f674e13..20d4271 100644 (file)
--- a/bfd/elfxx-mips.c
+++ b/bfd/elfxx-mips.c
@@ -5221,6 +5221,12 @@ _bfd_elf_mips_mach (flagword flags)
     case E_MIPS_MACH_SB1:
       return bfd_mach_mips_sb1;
 
+    case E_MIPS_MACH_LS2E:
+      return bfd_mach_mips_loongson_2e;
+
+    case E_MIPS_MACH_LS2F:
+      return bfd_mach_mips_loongson_2f;
+
     default:
       switch (flags & EF_MIPS_ARCH)
        {
@@ -9462,6 +9468,14 @@ mips_set_isa_flags (bfd *abfd)
       val = E_MIPS_ARCH_5;
       break;
 
+    case bfd_mach_mips_loongson_2e:
+      val = E_MIPS_ARCH_3 | E_MIPS_MACH_LS2E;
+      break;
+
+    case bfd_mach_mips_loongson_2f:
+      val = E_MIPS_ARCH_3 | E_MIPS_MACH_LS2F;
+      break;
+
     case bfd_mach_mips_sb1:
       val = E_MIPS_ARCH_64 | E_MIPS_MACH_SB1;
       break;
@@ -11228,6 +11242,8 @@ static const struct mips_mach_extension mips_mach_extensions[] = {
   { bfd_mach_mips4111, bfd_mach_mips4100 },
 
   /* MIPS III extensions.  */
+  { bfd_mach_mips_loongson_2e, bfd_mach_mips4000 },
+  { bfd_mach_mips_loongson_2f, bfd_mach_mips4000 },
   { bfd_mach_mips8000, bfd_mach_mips4000 },
   { bfd_mach_mips4650, bfd_mach_mips4000 },
   { bfd_mach_mips4600, bfd_mach_mips4000 },

diff --git a/binutils/ChangeLog b/binutils/ChangeLog
index 4b8025b..cce3880 100644 (file)
--- a/binutils/ChangeLog
+++ b/binutils/ChangeLog
@@ -1,3 +1,8 @@
+2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
+
+       * readelf.c (get_machine_flags): Handle Loongson-2E and -2F
+       flags.
+
 2007-11-26  Alan Modra  <amodra@bigpond.net.au>
 
        * cxxfilt.c (demangle_it): Don't call printf without format string.

diff --git a/binutils/readelf.c b/binutils/readelf.c
index d1e4de8..e827e6c 100644 (file)
--- a/binutils/readelf.c
+++ b/binutils/readelf.c
@@ -2194,6 +2194,8 @@ get_machine_flags (unsigned e_flags, unsigned e_machine)
            case E_MIPS_MACH_5500: strcat (buf, ", 5500"); break;
            case E_MIPS_MACH_SB1:  strcat (buf, ", sb1");  break;
            case E_MIPS_MACH_9000: strcat (buf, ", 9000"); break;
+           case E_MIPS_MACH_LS2E: strcat (buf, ", loongson-2e"); break;
+           case E_MIPS_MACH_LS2F: strcat (buf, ", loongson-2f"); break;
            case 0:
            /* We simply ignore the field in this case to avoid confusion:
               MIPS ELF does not specify EF_MIPS_MACH, it is a GNU

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 9d32ba2..1750ea3 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,9 @@
+2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
+
+       * config/tc-mips.c (mips_cpu_info_table): Add loongson2e
+       and loongson2f entries.
+       * doc/c-mips.texi: Document -march=loongson{2e,2f} options.
+
 2007-11-29  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 
        * config/tc-s390.c (md_begin): If the -mesa option is specified

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index dfc1646..7a88608 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -14823,6 +14823,10 @@ static const struct mips_cpu_info mips_cpu_info_table[] =
   { "sb1a",           MIPS_CPU_ASE_MIPS3D | MIPS_CPU_ASE_MDMX,
                                                ISA_MIPS64,     CPU_SB1 },
 
+  /* ST Microelectronics Loongson 2E and 2F cores */
+  { "loongson2e",     0,      ISA_MIPS3,      CPU_LOONGSON_2E },
+  { "loongson2f",     0,      ISA_MIPS3,      CPU_LOONGSON_2F },
+
   /* End marker */
   { NULL, 0, 0, 0 }
 };

diff --git a/gas/doc/c-mips.texi b/gas/doc/c-mips.texi
index 9f19726..e6fe033 100644 (file)
--- a/gas/doc/c-mips.texi
+++ b/gas/doc/c-mips.texi
@@ -270,7 +270,9 @@ m4kp,
 20kc,
 25kf,
 sb1,
-sb1a
+sb1a,
+loongson2e,
+loongson2f
 @end quotation
 
 For compatibility reasons, @samp{@var{n}x} and @samp{@var{b}fx} are

diff --git a/gas/testsuite/ChangeLog b/gas/testsuite/ChangeLog
index 47dba46..266c88d 100644 (file)
--- a/gas/testsuite/ChangeLog
+++ b/gas/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
+
+       * config/tc-mips.c (mips_cpu_info_table): Add loongson2e
+       and loongson2f entries.
+       * doc/c-mips.texi: Document -march=loongson{2e,2f} options.
+
 2007-11-29  Martin Schwidefsky  <schwidefsky@de.ibm.com>
 
        * gas/s390/esa-z9-109.d: Add check for old version of sske.

diff --git a/gas/testsuite/gas/mips/loongson-2e.d b/gas/testsuite/gas/mips/loongson-2e.d
new file mode 100644 (file)
index 0000000..59bf099
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-2e.d
@@ -0,0 +1,150 @@
+#as: -march=loongson2e -mabi=o64
+#objdump: -M reg-names=numeric -dr
+#name: ST Microelectronics Loongson-2E tests
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <movz_insns>:
+.*:    0064100a        movz    \$2,\$3,\$4
+.*:    0064100b        movn    \$2,\$3,\$4
+.*:    0064100b        movn    \$2,\$3,\$4
+
+[0-9a-f]+ <integer_insns>:
+.*:    7c641018        mult.g  \$2,\$3,\$4
+.*:    7cc72819        multu.g \$5,\$6,\$7
+.*:    7d2a401c        dmult.g \$8,\$9,\$10
+.*:    7d8d581d        dmultu.g        \$11,\$12,\$13
+.*:    7df0701a        div.g   \$14,\$15,\$16
+.*:    7e53881b        divu.g  \$17,\$18,\$19
+.*:    7eb6a01e        ddiv.g  \$20,\$21,\$22
+.*:    7f19b81f        ddivu.g \$23,\$24,\$25
+.*:    7f7cd022        mod.g   \$26,\$27,\$28
+.*:    7fdfe823        modu.g  \$29,\$30,\$31
+.*:    7c641026        dmod.g  \$2,\$3,\$4
+.*:    7cc72827        dmodu.g \$5,\$6,\$7
+
+[0-9a-f]+ <fpu_insns>:
+.*:    46020818        madd.s  \$f0,\$f1,\$f2
+.*:    462520d8        madd.d  \$f3,\$f4,\$f5
+.*:    45683998        madd.ps \$f6,\$f7,\$f8
+.*:    460b5259        msub.s  \$f9,\$f10,\$f11
+.*:    462e6b19        msub.d  \$f12,\$f13,\$f14
+.*:    457183d9        msub.ps \$f15,\$f16,\$f17
+.*:    46149c9a        nmadd.s \$f18,\$f19,\$f20
+.*:    4637b55a        nmadd.d \$f21,\$f22,\$f23
+.*:    457ace1a        nmadd.ps        \$f24,\$f25,\$f26
+.*:    461de6db        nmsub.s \$f27,\$f28,\$f29
+.*:    4622081b        nmsub.d \$f0,\$f1,\$f2
+.*:    456520db        nmsub.ps        \$f3,\$f4,\$f5
+
+[0-9a-f]+ <simd_insns>:
+.*:    47420802        packsshb        \$f0,\$f1,\$f2
+.*:    472520c2        packsswh        \$f3,\$f4,\$f5
+.*:    47683982        packushb        \$f6,\$f7,\$f8
+.*:    47cb5240        paddb   \$f9,\$f10,\$f11
+.*:    474e6b00        paddh   \$f12,\$f13,\$f14
+.*:    477183c0        paddw   \$f15,\$f16,\$f17
+.*:    47f49c80        paddd   \$f18,\$f19,\$f20
+.*:    4797b540        paddsb  \$f21,\$f22,\$f23
+.*:    471ace00        paddsh  \$f24,\$f25,\$f26
+.*:    47bde6c0        paddusb \$f27,\$f28,\$f29
+.*:    47220800        paddush \$f0,\$f1,\$f2
+.*:    47e520c2        pandn   \$f3,\$f4,\$f5
+.*:    46683980        pavgb   \$f6,\$f7,\$f8
+.*:    464b5240        pavgh   \$f9,\$f10,\$f11
+.*:    46ce6b01        pcmpeqb \$f12,\$f13,\$f14
+.*:    469183c1        pcmpeqh \$f15,\$f16,\$f17
+.*:    46549c81        pcmpeqw \$f18,\$f19,\$f20
+.*:    46f7b541        pcmpgtb \$f21,\$f22,\$f23
+.*:    46bace01        pcmpgth \$f24,\$f25,\$f26
+.*:    467de6c1        pcmpgtw \$f27,\$f28,\$f29
+.*:    45c20802        pextrh  \$f0,\$f1,\$f2
+.*:    478520c3        pinsrh_0        \$f3,\$f4,\$f5
+.*:    47a83983        pinsrh_1        \$f6,\$f7,\$f8
+.*:    47cb5243        pinsrh_2        \$f9,\$f10,\$f11
+.*:    47ee6b03        pinsrh_3        \$f12,\$f13,\$f14
+.*:    45f183c2        pmaddhw \$f15,\$f16,\$f17
+.*:    46949c80        pmaxsh  \$f18,\$f19,\$f20
+.*:    46d7b540        pmaxub  \$f21,\$f22,\$f23
+.*:    46bace00        pminsh  \$f24,\$f25,\$f26
+.*:    46fde6c0        pminub  \$f27,\$f28,\$f29
+.*:    46a00805        pmovmskb        \$f0,\$f1
+.*:    46e41882        pmulhuh \$f2,\$f3,\$f4
+.*:    46a73142        pmulhh  \$f5,\$f6,\$f7
+.*:    468a4a02        pmullh  \$f8,\$f9,\$f10
+.*:    46cd62c2        pmuluw  \$f11,\$f12,\$f13
+.*:    45b07b81        pasubub \$f14,\$f15,\$f16
+.*:    46809445        biadd   \$f17,\$f18
+.*:    4715a4c2        pshufh  \$f19,\$f20,\$f21
+.*:    4678bd82        psllh   \$f22,\$f23,\$f24
+.*:    465bd642        psllw   \$f25,\$f26,\$f27
+.*:    46beef03        psrah   \$f28,\$f29,\$f30
+.*:    46820803        psraw   \$f0,\$f1,\$f2
+.*:    466520c3        psrlh   \$f3,\$f4,\$f5
+.*:    46483983        psrlw   \$f6,\$f7,\$f8
+.*:    47cb5241        psubb   \$f9,\$f10,\$f11
+.*:    474e6b01        psubh   \$f12,\$f13,\$f14
+.*:    477183c1        psubw   \$f15,\$f16,\$f17
+.*:    47f49c81        psubd   \$f18,\$f19,\$f20
+.*:    4797b541        psubsb  \$f21,\$f22,\$f23
+.*:    471ace01        psubsh  \$f24,\$f25,\$f26
+.*:    47bde6c1        psubusb \$f27,\$f28,\$f29
+.*:    47220801        psubush \$f0,\$f1,\$f2
+.*:    476520c3        punpckhbh       \$f3,\$f4,\$f5
+.*:    47283983        punpckhhw       \$f6,\$f7,\$f8
+.*:    46eb5243        punpckhwd       \$f9,\$f10,\$f11
+.*:    474e6b03        punpcklbh       \$f12,\$f13,\$f14
+.*:    471183c3        punpcklhw       \$f15,\$f16,\$f17
+.*:    46d49c83        punpcklwd       \$f18,\$f19,\$f20
+
+[0-9a-f]+ <fixed_point_insns>:
+.*:    45c20800        add     \$f0,\$f1,\$f2
+.*:    458520c0        addu    \$f3,\$f4,\$f5
+.*:    45e83980        dadd    \$f6,\$f7,\$f8
+.*:    45cb5241        sub     \$f9,\$f10,\$f11
+.*:    458e6b01        subu    \$f12,\$f13,\$f14
+.*:    45f183c1        dsub    \$f15,\$f16,\$f17
+.*:    45b49c80        or      \$f18,\$f19,\$f20
+.*:    4597b542        sll     \$f21,\$f22,\$f23
+.*:    45bace02        dsll    \$f24,\$f25,\$f26
+.*:    479de6c2        xor     \$f27,\$f28,\$f29
+.*:    47a20802        nor     \$f0,\$f1,\$f2
+.*:    47c520c2        and     \$f3,\$f4,\$f5
+.*:    45883983        srl     \$f6,\$f7,\$f8
+.*:    45ab5243        dsrl    \$f9,\$f10,\$f11
+.*:    45ce6b03        sra     \$f12,\$f13,\$f14
+.*:    45f183c3        dsra    \$f15,\$f16,\$f17
+.*:    46939032        sequ    \$f18,\$f19
+.*:    4695a03c        sltu    \$f20,\$f21
+.*:    4697b03e        sleu    \$f22,\$f23
+.*:    46b9c032        seq     \$f24,\$f25
+.*:    46bbd03c        slt     \$f26,\$f27
+.*:    46bde03e        sle     \$f28,\$f29
+
+[0-9a-f]+ <mips5_ps_insns>:
+.*:    45601005        abs.ps  \$f0,\$f2
+.*:    45662080        add.ps  \$f2,\$f4,\$f6
+.*:    456a4032        c.eq.ps \$f8,\$f10
+.*:    456a4030        c.f.ps  \$f8,\$f10
+.*:    456a403e        c.le.ps \$f8,\$f10
+.*:    456a403c        c.lt.ps \$f8,\$f10
+.*:    456a403d        c.nge.ps        \$f8,\$f10
+.*:    456a403b        c.ngl.ps        \$f8,\$f10
+.*:    456a4039        c.ngle.ps       \$f8,\$f10
+.*:    456a403f        c.ngt.ps        \$f8,\$f10
+.*:    456a4036        c.ole.ps        \$f8,\$f10
+.*:    456a4034        c.olt.ps        \$f8,\$f10
+.*:    456a403a        c.seq.ps        \$f8,\$f10
+.*:    456a4038        c.sf.ps \$f8,\$f10
+.*:    456a4033        c.ueq.ps        \$f8,\$f10
+.*:    456a4037        c.ule.ps        \$f8,\$f10
+.*:    456a4035        c.ult.ps        \$f8,\$f10
+.*:    456a4031        c.un.ps \$f8,\$f10
+.*:    4560d606        mov.ps  \$f24,\$f26
+.*:    45662082        mul.ps  \$f2,\$f4,\$f6
+.*:    45604187        neg.ps  \$f6,\$f8
+.*:    457ac581        sub.ps  \$f22,\$f24,\$f26
+#pass
+

diff --git a/gas/testsuite/gas/mips/loongson-2e.s b/gas/testsuite/gas/mips/loongson-2e.s
new file mode 100644 (file)
index 0000000..ceca517
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-2e.s
@@ -0,0 +1,144 @@
+        .text
+       .set noreorder
+
+movz_insns:
+       movz            $2, $3, $4
+       movnz           $2, $3, $4
+       movn            $2, $3, $4
+
+integer_insns:
+       mult.g          $2, $3, $4
+       multu.g         $5, $6, $7
+       dmult.g         $8, $9, $10
+       dmultu.g        $11, $12, $13
+       div.g           $14, $15, $16
+       divu.g          $17, $18, $19
+       ddiv.g          $20, $21, $22
+       ddivu.g         $23, $24, $25
+       mod.g           $26, $27, $28
+       modu.g          $29, $30, $31
+       dmod.g          $2, $3, $4
+       dmodu.g         $5, $6, $7
+
+fpu_insns:
+       madd.s          $f0, $f1, $f2
+       madd.d          $f3, $f4, $f5
+       madd.ps         $f6, $f7, $f8
+       msub.s          $f9, $f10, $f11
+       msub.d          $f12, $f13, $f14
+       msub.ps         $f15, $f16, $f17
+       nmadd.s         $f18, $f19, $f20
+       nmadd.d         $f21, $f22, $f23
+       nmadd.ps        $f24, $f25, $f26
+       nmsub.s         $f27, $f28, $f29
+       nmsub.d         $f0, $f1, $f2
+       nmsub.ps        $f3, $f4, $f5
+
+simd_insns:
+       packsshb        $f0, $f1, $f2
+       packsswh        $f3, $f4, $f5
+       packushb        $f6, $f7, $f8
+       paddb           $f9, $f10, $f11
+       paddh           $f12, $f13, $f14
+       paddw           $f15, $f16, $f17
+       paddd           $f18, $f19, $f20
+       paddsb          $f21, $f22, $f23
+       paddsh          $f24, $f25, $f26
+       paddusb         $f27, $f28, $f29
+       paddush         $f0, $f1, $f2
+       pandn           $f3, $f4, $f5
+       pavgb           $f6, $f7, $f8
+       pavgh           $f9, $f10, $f11
+       pcmpeqb         $f12, $f13, $f14
+       pcmpeqh         $f15, $f16, $f17
+       pcmpeqw         $f18, $f19, $f20
+       pcmpgtb         $f21, $f22, $f23
+       pcmpgth         $f24, $f25, $f26
+       pcmpgtw         $f27, $f28, $f29
+       pextrh          $f0, $f1, $f2
+       pinsrh_0        $f3, $f4, $f5
+       pinsrh_1        $f6, $f7, $f8
+       pinsrh_2        $f9, $f10, $f11
+       pinsrh_3        $f12, $f13, $f14
+       pmaddhw         $f15, $f16, $f17
+       pmaxsh          $f18, $f19, $f20
+       pmaxub          $f21, $f22, $f23
+       pminsh          $f24, $f25, $f26
+       pminub          $f27, $f28, $f29
+       pmovmskb        $f0, $f1
+       pmulhuh         $f2, $f3, $f4
+       pmulhh          $f5, $f6, $f7
+       pmullh          $f8, $f9, $f10
+       pmuluw          $f11, $f12, $f13
+       pasubub         $f14, $f15, $f16
+       biadd           $f17, $f18
+       pshufh          $f19, $f20, $f21
+       psllh           $f22, $f23, $f24
+       psllw           $f25, $f26, $f27
+       psrah           $f28, $f29, $f30
+       psraw           $f0, $f1, $f2
+       psrlh           $f3, $f4, $f5
+       psrlw           $f6, $f7, $f8
+       psubb           $f9, $f10, $f11
+       psubh           $f12, $f13, $f14
+       psubw           $f15, $f16, $f17
+       psubd           $f18, $f19, $f20
+       psubsb          $f21, $f22, $f23
+       psubsh          $f24, $f25, $f26
+       psubusb         $f27, $f28, $f29
+       psubush         $f0, $f1, $f2
+       punpckhbh       $f3, $f4, $f5
+       punpckhhw       $f6, $f7, $f8
+       punpckhwd       $f9, $f10, $f11
+       punpcklbh       $f12, $f13, $f14
+       punpcklhw       $f15, $f16, $f17
+       punpcklwd       $f18, $f19, $f20
+
+fixed_point_insns:
+       add             $f0, $f1, $f2
+       addu            $f3, $f4, $f5
+       dadd            $f6, $f7, $f8
+       sub             $f9, $f10, $f11
+       subu            $f12, $f13, $f14
+       dsub            $f15, $f16, $f17
+       or              $f18, $f19, $f20
+       sll             $f21, $f22, $f23
+       dsll            $f24, $f25, $f26
+       xor             $f27, $f28, $f29
+       nor             $f0, $f1, $f2
+       and             $f3, $f4, $f5
+       srl             $f6, $f7, $f8
+       dsrl            $f9, $f10, $f11
+       sra             $f12, $f13, $f14
+       dsra            $f15, $f16, $f17
+       sequ            $f18, $f19
+       sltu            $f20, $f21
+       sleu            $f22, $f23
+       seq             $f24, $f25
+       slt             $f26, $f27
+       sle             $f28, $f29
+
+mips5_ps_insns:
+       abs.ps          $f0, $f2
+       add.ps          $f2, $f4, $f6
+       c.eq.ps         $f8, $f10
+       c.f.ps          $f8, $f10
+       c.le.ps         $f8, $f10
+       c.lt.ps         $f8, $f10
+       c.nge.ps        $f8, $f10
+       c.ngl.ps        $f8, $f10
+       c.ngle.ps       $f8, $f10
+       c.ngt.ps        $f8, $f10
+       c.ole.ps        $f8, $f10
+       c.olt.ps        $f8, $f10
+       c.seq.ps        $f8, $f10
+       c.sf.ps         $f8, $f10
+       c.ueq.ps        $f8, $f10
+       c.ule.ps        $f8, $f10
+       c.ult.ps        $f8, $f10
+       c.un.ps         $f8, $f10
+       mov.ps          $f24, $f26
+       mul.ps          $f2, $f4, $f6
+       neg.ps          $f6, $f8
+       sub.ps          $f22, $f24, $f26
+

diff --git a/gas/testsuite/gas/mips/loongson-2f.d b/gas/testsuite/gas/mips/loongson-2f.d
new file mode 100644 (file)
index 0000000..a47441a
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-2f.d
@@ -0,0 +1,150 @@
+#as: -march=loongson2f -mabi=o64
+#objdump: -M reg-names=numeric -dr
+#name: ST Microelectronics Loongson-2F tests
+
+.*:     file format .*
+
+Disassembly of section .text:
+
+[0-9a-f]+ <movz_insns>:
+.*:    0064100a        movz    \$2,\$3,\$4
+.*:    0064100b        movn    \$2,\$3,\$4
+.*:    0064100b        movn    \$2,\$3,\$4
+
+[0-9a-f]+ <integer_insns>:
+.*:    70641010        mult.g  \$2,\$3,\$4
+.*:    70c72812        multu.g \$5,\$6,\$7
+.*:    712a4011        dmult.g \$8,\$9,\$10
+.*:    718d5813        dmultu.g        \$11,\$12,\$13
+.*:    71f07014        div.g   \$14,\$15,\$16
+.*:    72538816        divu.g  \$17,\$18,\$19
+.*:    72b6a015        ddiv.g  \$20,\$21,\$22
+.*:    7319b817        ddivu.g \$23,\$24,\$25
+.*:    737cd01c        mod.g   \$26,\$27,\$28
+.*:    73dfe81e        modu.g  \$29,\$30,\$31
+.*:    7064101d        dmod.g  \$2,\$3,\$4
+.*:    70c7281f        dmodu.g \$5,\$6,\$7
+
+[0-9a-f]+ <fpu_insns>:
+.*:    72020818        madd.s  \$f0,\$f1,\$f2
+.*:    722520d8        madd.d  \$f3,\$f4,\$f5
+.*:    71683998        madd.ps \$f6,\$f7,\$f8
+.*:    720b5259        msub.s  \$f9,\$f10,\$f11
+.*:    722e6b19        msub.d  \$f12,\$f13,\$f14
+.*:    717183d9        msub.ps \$f15,\$f16,\$f17
+.*:    72149c9a        nmadd.s \$f18,\$f19,\$f20
+.*:    7237b55a        nmadd.d \$f21,\$f22,\$f23
+.*:    717ace1a        nmadd.ps        \$f24,\$f25,\$f26
+.*:    721de6db        nmsub.s \$f27,\$f28,\$f29
+.*:    7222081b        nmsub.d \$f0,\$f1,\$f2
+.*:    716520db        nmsub.ps        \$f3,\$f4,\$f5
+
+[0-9a-f]+ <simd_insns>:
+.*:    4b420802        packsshb        \$f0,\$f1,\$f2
+.*:    4b2520c2        packsswh        \$f3,\$f4,\$f5
+.*:    4b683982        packushb        \$f6,\$f7,\$f8
+.*:    4bcb5240        paddb   \$f9,\$f10,\$f11
+.*:    4b4e6b00        paddh   \$f12,\$f13,\$f14
+.*:    4b7183c0        paddw   \$f15,\$f16,\$f17
+.*:    4bf49c80        paddd   \$f18,\$f19,\$f20
+.*:    4b97b540        paddsb  \$f21,\$f22,\$f23
+.*:    4b1ace00        paddsh  \$f24,\$f25,\$f26
+.*:    4bbde6c0        paddusb \$f27,\$f28,\$f29
+.*:    4b220800        paddush \$f0,\$f1,\$f2
+.*:    4be520c2        pandn   \$f3,\$f4,\$f5
+.*:    4b283988        pavgb   \$f6,\$f7,\$f8
+.*:    4b0b5248        pavgh   \$f9,\$f10,\$f11
+.*:    4b8e6b09        pcmpeqb \$f12,\$f13,\$f14
+.*:    4b5183c9        pcmpeqh \$f15,\$f16,\$f17
+.*:    4b149c89        pcmpeqw \$f18,\$f19,\$f20
+.*:    4bb7b549        pcmpgtb \$f21,\$f22,\$f23
+.*:    4b7ace09        pcmpgth \$f24,\$f25,\$f26
+.*:    4b3de6c9        pcmpgtw \$f27,\$f28,\$f29
+.*:    4b42080e        pextrh  \$f0,\$f1,\$f2
+.*:    4b8520c3        pinsrh_0        \$f3,\$f4,\$f5
+.*:    4ba83983        pinsrh_1        \$f6,\$f7,\$f8
+.*:    4bcb5243        pinsrh_2        \$f9,\$f10,\$f11
+.*:    4bee6b03        pinsrh_3        \$f12,\$f13,\$f14
+.*:    4b7183ce        pmaddhw \$f15,\$f16,\$f17
+.*:    4b549c88        pmaxsh  \$f18,\$f19,\$f20
+.*:    4b97b548        pmaxub  \$f21,\$f22,\$f23
+.*:    4b7ace08        pminsh  \$f24,\$f25,\$f26
+.*:    4bbde6c8        pminub  \$f27,\$f28,\$f29
+.*:    4ba0080f        pmovmskb        \$f0,\$f1
+.*:    4ba4188a        pmulhuh \$f2,\$f3,\$f4
+.*:    4b67314a        pmulhh  \$f5,\$f6,\$f7
+.*:    4b4a4a0a        pmullh  \$f8,\$f9,\$f10
+.*:    4b8d62ca        pmuluw  \$f11,\$f12,\$f13
+.*:    4b307b8d        pasubub \$f14,\$f15,\$f16
+.*:    4b80944f        biadd   \$f17,\$f18
+.*:    4b15a4c2        pshufh  \$f19,\$f20,\$f21
+.*:    4b38bd8a        psllh   \$f22,\$f23,\$f24
+.*:    4b1bd64a        psllw   \$f25,\$f26,\$f27
+.*:    4b7eef0b        psrah   \$f28,\$f29,\$f30
+.*:    4b42080b        psraw   \$f0,\$f1,\$f2
+.*:    4b2520cb        psrlh   \$f3,\$f4,\$f5
+.*:    4b08398b        psrlw   \$f6,\$f7,\$f8
+.*:    4bcb5241        psubb   \$f9,\$f10,\$f11
+.*:    4b4e6b01        psubh   \$f12,\$f13,\$f14
+.*:    4b7183c1        psubw   \$f15,\$f16,\$f17
+.*:    4bf49c81        psubd   \$f18,\$f19,\$f20
+.*:    4b97b541        psubsb  \$f21,\$f22,\$f23
+.*:    4b1ace01        psubsh  \$f24,\$f25,\$f26
+.*:    4bbde6c1        psubusb \$f27,\$f28,\$f29
+.*:    4b220801        psubush \$f0,\$f1,\$f2
+.*:    4b6520c3        punpckhbh       \$f3,\$f4,\$f5
+.*:    4b283983        punpckhhw       \$f6,\$f7,\$f8
+.*:    4bab524b        punpckhwd       \$f9,\$f10,\$f11
+.*:    4b4e6b03        punpcklbh       \$f12,\$f13,\$f14
+.*:    4b1183c3        punpcklhw       \$f15,\$f16,\$f17
+.*:    4b949c8b        punpcklwd       \$f18,\$f19,\$f20
+
+[0-9a-f]+ <fixed_point_insns>:
+.*:    4b42080c        add     \$f0,\$f1,\$f2
+.*:    4b0520cc        addu    \$f3,\$f4,\$f5
+.*:    4b68398c        dadd    \$f6,\$f7,\$f8
+.*:    4b4b524d        sub     \$f9,\$f10,\$f11
+.*:    4b0e6b0d        subu    \$f12,\$f13,\$f14
+.*:    4b7183cd        dsub    \$f15,\$f16,\$f17
+.*:    4b349c8c        or      \$f18,\$f19,\$f20
+.*:    4b17b54e        sll     \$f21,\$f22,\$f23
+.*:    4b3ace0e        dsll    \$f24,\$f25,\$f26
+.*:    4b9de6c2        xor     \$f27,\$f28,\$f29
+.*:    4ba20802        nor     \$f0,\$f1,\$f2
+.*:    4bc520c2        and     \$f3,\$f4,\$f5
+.*:    4b08398f        srl     \$f6,\$f7,\$f8
+.*:    4b2b524f        dsrl    \$f9,\$f10,\$f11
+.*:    4b4e6b0f        sra     \$f12,\$f13,\$f14
+.*:    4b7183cf        dsra    \$f15,\$f16,\$f17
+.*:    4b93900c        sequ    \$f18,\$f19
+.*:    4b95a00d        sltu    \$f20,\$f21
+.*:    4b97b00e        sleu    \$f22,\$f23
+.*:    4bb9c00c        seq     \$f24,\$f25
+.*:    4bbbd00d        slt     \$f26,\$f27
+.*:    4bbde00e        sle     \$f28,\$f29
+
+000001ac <mips5_ps_insns>:
+.*:    46c01005        abs.ps  \$f0,\$f2
+.*:    46c62080        add.ps  \$f2,\$f4,\$f6
+.*:    46ca4032        c.eq.ps \$f8,\$f10
+.*:    46ca4030        c.f.ps  \$f8,\$f10
+.*:    46ca403e        c.le.ps \$f8,\$f10
+.*:    46ca403c        c.lt.ps \$f8,\$f10
+.*:    46ca403d        c.nge.ps        \$f8,\$f10
+.*:    46ca403b        c.ngl.ps        \$f8,\$f10
+.*:    46ca4039        c.ngle.ps       \$f8,\$f10
+.*:    46ca403f        c.ngt.ps        \$f8,\$f10
+.*:    46ca4036        c.ole.ps        \$f8,\$f10
+.*:    46ca4034        c.olt.ps        \$f8,\$f10
+.*:    46ca403a        c.seq.ps        \$f8,\$f10
+.*:    46ca4038        c.sf.ps \$f8,\$f10
+.*:    46ca4033        c.ueq.ps        \$f8,\$f10
+.*:    46ca4037        c.ule.ps        \$f8,\$f10
+.*:    46ca4035        c.ult.ps        \$f8,\$f10
+.*:    46ca4031        c.un.ps \$f8,\$f10
+.*:    46c0d606        mov.ps  \$f24,\$f26
+.*:    46c62082        mul.ps  \$f2,\$f4,\$f6
+.*:    46c04187        neg.ps  \$f6,\$f8
+.*:    46dac581        sub.ps  \$f22,\$f24,\$f26
+#pass
+

diff --git a/gas/testsuite/gas/mips/loongson-2f.s b/gas/testsuite/gas/mips/loongson-2f.s
new file mode 100644 (file)
index 0000000..4b47a99
--- /dev/null
+++ b/gas/testsuite/gas/mips/loongson-2f.s
@@ -0,0 +1,144 @@
+       .text
+       .set noreorder
+
+movz_insns:
+       movz            $2, $3, $4
+       movnz           $2, $3, $4
+       movn            $2, $3, $4
+
+integer_insns:
+       mult.g          $2, $3, $4
+       multu.g         $5, $6, $7
+       dmult.g         $8, $9, $10
+       dmultu.g        $11, $12, $13
+       div.g           $14, $15, $16
+       divu.g          $17, $18, $19
+       ddiv.g          $20, $21, $22
+       ddivu.g         $23, $24, $25
+       mod.g           $26, $27, $28
+       modu.g          $29, $30, $31
+       dmod.g          $2, $3, $4
+       dmodu.g         $5, $6, $7
+
+fpu_insns:
+       madd.s          $f0, $f1, $f2
+       madd.d          $f3, $f4, $f5
+       madd.ps         $f6, $f7, $f8
+       msub.s          $f9, $f10, $f11
+       msub.d          $f12, $f13, $f14
+       msub.ps         $f15, $f16, $f17
+       nmadd.s         $f18, $f19, $f20
+       nmadd.d         $f21, $f22, $f23
+       nmadd.ps        $f24, $f25, $f26
+       nmsub.s         $f27, $f28, $f29
+       nmsub.d         $f0, $f1, $f2
+       nmsub.ps        $f3, $f4, $f5
+
+simd_insns:
+       packsshb        $f0, $f1, $f2
+       packsswh        $f3, $f4, $f5
+       packushb        $f6, $f7, $f8
+       paddb           $f9, $f10, $f11
+       paddh           $f12, $f13, $f14
+       paddw           $f15, $f16, $f17
+       paddd           $f18, $f19, $f20
+       paddsb          $f21, $f22, $f23
+       paddsh          $f24, $f25, $f26
+       paddusb         $f27, $f28, $f29
+       paddush         $f0, $f1, $f2
+       pandn           $f3, $f4, $f5
+       pavgb           $f6, $f7, $f8
+       pavgh           $f9, $f10, $f11
+       pcmpeqb         $f12, $f13, $f14
+       pcmpeqh         $f15, $f16, $f17
+       pcmpeqw         $f18, $f19, $f20
+       pcmpgtb         $f21, $f22, $f23
+       pcmpgth         $f24, $f25, $f26
+       pcmpgtw         $f27, $f28, $f29
+       pextrh          $f0, $f1, $f2
+       pinsrh_0        $f3, $f4, $f5
+       pinsrh_1        $f6, $f7, $f8
+       pinsrh_2        $f9, $f10, $f11
+       pinsrh_3        $f12, $f13, $f14
+       pmaddhw         $f15, $f16, $f17
+       pmaxsh          $f18, $f19, $f20
+       pmaxub          $f21, $f22, $f23
+       pminsh          $f24, $f25, $f26
+       pminub          $f27, $f28, $f29
+       pmovmskb        $f0, $f1
+       pmulhuh         $f2, $f3, $f4
+       pmulhh          $f5, $f6, $f7
+       pmullh          $f8, $f9, $f10
+       pmuluw          $f11, $f12, $f13
+       pasubub         $f14, $f15, $f16
+       biadd           $f17, $f18
+       pshufh          $f19, $f20, $f21
+       psllh           $f22, $f23, $f24
+       psllw           $f25, $f26, $f27
+       psrah           $f28, $f29, $f30
+       psraw           $f0, $f1, $f2
+       psrlh           $f3, $f4, $f5
+       psrlw           $f6, $f7, $f8
+       psubb           $f9, $f10, $f11
+       psubh           $f12, $f13, $f14
+       psubw           $f15, $f16, $f17
+       psubd           $f18, $f19, $f20
+       psubsb          $f21, $f22, $f23
+       psubsh          $f24, $f25, $f26
+       psubusb         $f27, $f28, $f29
+       psubush         $f0, $f1, $f2
+       punpckhbh       $f3, $f4, $f5
+       punpckhhw       $f6, $f7, $f8
+       punpckhwd       $f9, $f10, $f11
+       punpcklbh       $f12, $f13, $f14
+       punpcklhw       $f15, $f16, $f17
+       punpcklwd       $f18, $f19, $f20
+
+fixed_point_insns:
+       add             $f0, $f1, $f2
+       addu            $f3, $f4, $f5
+       dadd            $f6, $f7, $f8
+       sub             $f9, $f10, $f11
+       subu            $f12, $f13, $f14
+       dsub            $f15, $f16, $f17
+       or              $f18, $f19, $f20
+       sll             $f21, $f22, $f23
+       dsll            $f24, $f25, $f26
+       xor             $f27, $f28, $f29
+       nor             $f0, $f1, $f2
+       and             $f3, $f4, $f5
+       srl             $f6, $f7, $f8
+       dsrl            $f9, $f10, $f11
+       sra             $f12, $f13, $f14
+       dsra            $f15, $f16, $f17
+       sequ            $f18, $f19
+       sltu            $f20, $f21
+       sleu            $f22, $f23
+       seq             $f24, $f25
+       slt             $f26, $f27
+       sle             $f28, $f29
+
+mips5_ps_insns:
+       abs.ps          $f0, $f2
+       add.ps          $f2, $f4, $f6
+       c.eq.ps         $f8, $f10
+       c.f.ps          $f8, $f10
+       c.le.ps         $f8, $f10
+       c.lt.ps         $f8, $f10
+       c.nge.ps        $f8, $f10
+       c.ngl.ps        $f8, $f10
+       c.ngle.ps       $f8, $f10
+       c.ngt.ps        $f8, $f10
+       c.ole.ps        $f8, $f10
+       c.olt.ps        $f8, $f10
+       c.seq.ps        $f8, $f10
+       c.sf.ps         $f8, $f10
+       c.ueq.ps        $f8, $f10
+       c.ule.ps        $f8, $f10
+       c.ult.ps        $f8, $f10
+       c.un.ps         $f8, $f10
+       mov.ps          $f24, $f26
+       mul.ps          $f2, $f4, $f6
+       neg.ps          $f6, $f8
+       sub.ps          $f22, $f24, $f26
+

diff --git a/gas/testsuite/gas/mips/mips.exp b/gas/testsuite/gas/mips/mips.exp
index 30efee8..5d04f41 100644 (file)
--- a/gas/testsuite/gas/mips/mips.exp
+++ b/gas/testsuite/gas/mips/mips.exp
@@ -757,6 +757,9 @@ if { [istarget mips*-*-vxworks*] } {
     run_dump_test "at-1"
     run_list_test "at-2" "-32 -mips1" "MIPS at-2"
 
+    run_dump_test "loongson-2e"
+    run_dump_test "loongson-2f"
+
     run_dump_test_arches "smartmips"   [mips_arch_list_matching mips32 !gpr64]
     run_dump_test_arches "mips32-dsp"  [mips_arch_list_matching mips32r2]
     run_dump_test_arches "mips32-dspr2"        [mips_arch_list_matching mips32r2]

diff --git a/include/elf/ChangeLog b/include/elf/ChangeLog
index ded6712..dd46a11 100644 (file)
--- a/include/elf/ChangeLog
+++ b/include/elf/ChangeLog
@@ -1,3 +1,8 @@
+2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
+
+       * mips.h (E_MIPS_MACH_LS2E): New.
+       (E_MIPS_MACH_LS2F): New.
+
 2007-11-28  Nathan Sidwell  <nathan@codesourcery.com>
 
        * internal.h (ELF_IS_SECTION_IN_SEGMENT): Adjust to cope with

diff --git a/include/elf/mips.h b/include/elf/mips.h
index f54ef70..63a9718 100644 (file)
--- a/include/elf/mips.h
+++ b/include/elf/mips.h
@@ -216,6 +216,8 @@ END_RELOC_NUMBERS (R_MIPS_maxext)
 #define E_MIPS_MACH_5400       0x00910000
 #define E_MIPS_MACH_5500       0x00980000
 #define E_MIPS_MACH_9000       0x00990000
+#define E_MIPS_MACH_LS2E        0x00A00000
+#define E_MIPS_MACH_LS2F        0x00A10000
 \f
 /* Processor specific section indices.  These sections do not actually
    exist.  Symbols with a st_shndx field corresponding to one of these

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index dd37f6c..afd480b 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,5 +1,13 @@
 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 
+       * mips.h (INSN_LOONGSON_2E): New.
+       (INSN_LOONGSON_2F): New.
+       (CPU_LOONGSON_2E): New.
+       (CPU_LOONGSON_2F): New.
+       (OPCODE_IS_MEMBER): Update for Loongson-2E and -2F flags.
+
+2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
+
        * mips.h (INSN_ISA*): Redefine certain values as an
        enumeration.  Update comments.
        (mips_isa_table): New.

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index d74dccd..20638d8 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -552,6 +552,10 @@ static const unsigned int mips_isa_table[] =
 #define INSN_SMARTMIPS            0x10000000
 /* DSP R2 ASE  */
 #define INSN_DSPR2                0x20000000
+/* ST Microelectronics Loongson 2E.  */
+#define INSN_LOONGSON_2E          0x40000000
+/* ST Microelectronics Loongson 2F.  */
+#define INSN_LOONGSON_2F          0x80000000
 
 /* MIPS ISA defines, use instead of hardcoding ISA level.  */
 
@@ -599,6 +603,8 @@ static const unsigned int mips_isa_table[] =
 #define CPU_MIPS64      64
 #define CPU_MIPS64R2   65
 #define CPU_SB1         12310201        /* octal 'SB', 01.  */
+#define CPU_LOONGSON_2E 3001
+#define CPU_LOONGSON_2F 3002
 
 /* Test for membership in an ISA including chip specific ISAs.  INSN
    is pointer to an element of the opcode table; ISA is the specified
@@ -625,6 +631,10 @@ static const unsigned int mips_isa_table[] =
      || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0)   \
      || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0)   \
      || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0)   \
+     || (cpu == CPU_LOONGSON_2E                                         \
+         && ((insn)->membership & INSN_LOONGSON_2E) != 0)               \
+     || (cpu == CPU_LOONGSON_2F                                         \
+         && ((insn)->membership & INSN_LOONGSON_2F) != 0)               \
      || 0)     /* Please keep this term for easier source merging.  */
 
 /* This is a list of macro expanded instructions.

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index fa04b88..fb77bad 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,16 @@
 2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
 
+       * mips-dis.c (mips_arch_choices): Add Loongson-2E and -2F
+       entries.
+       * mips-opc.c (IL2E): New.
+       (IL2F): New.
+       (mips_builtin_opcodes): Add Loongson-2E and -2F instructions.
+       Allow movz and movn for Loongson-2E and -2F.  Add movnz entry.
+       Move coprocessor encodings to the end of the table.  Allow
+       certain MIPS V .ps instructions on the Loongson-2E and -2F.
+
+2007-11-29  Mark Shinwell  <shinwell@codesourcery.com>
+
        * mips-opc.c (I3_32, I3_33, I4_32, I4_33, I5_33): New.
        (mips_builtin_opcodes): Use these new I* values.
 

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 186646a..378847d 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -450,6 +450,14 @@ const struct mips_arch_choice mips_arch_choices[] =
     mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
     mips_hwr_names_numeric },
 
+  { "loongson2e",   1, bfd_mach_mips_loongson_2e, CPU_LOONGSON_2E,
+    ISA_MIPS3 | INSN_LOONGSON_2E, mips_cp0_names_numeric, 
+    NULL, 0, mips_hwr_names_numeric },
+
+  { "loongson2f",   1, bfd_mach_mips_loongson_2f, CPU_LOONGSON_2F,
+    ISA_MIPS3 | INSN_LOONGSON_2F, mips_cp0_names_numeric, 
+    NULL, 0, mips_hwr_names_numeric },
+
   /* This entry, mips16, is here only for ISA/processor selection; do
      not print its name.  */
   { "",                1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,

diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 0c30d65..746763b 100644 (file)
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -107,6 +107,9 @@
 /* MIPS64 MDMX ASE support.  */
 #define MX      INSN_MDMX
 
+#define IL2E    (INSN_LOONGSON_2E)
+#define IL2F    (INSN_LOONGSON_2F)
+
 #define P3     INSN_4650
 #define L1     INSN_4010
 #define V1     (INSN_4100 | INSN_4111 | INSN_4120)
@@ -198,16 +201,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"abs",     "d,v",     0,    (int) M_ABS,      INSN_MACRO,             0,              I1      },
 {"abs.s",   "D,V",     0x46000005, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
 {"abs.d",   "D,V",     0x46200005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
-{"abs.ps",  "D,V",     0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33   },
+{"abs.ps",  "D,V",     0x46c00005, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33|IL2F      },
+{"abs.ps",  "D,V",     0x45600005, 0xffff003f, WR_D|RD_S|FP_D,         0,              IL2E    },
 {"add",     "d,v,t",   0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"add",     "t,r,I",   0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1      },
+{"add",        "D,S,T",        0x45c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"add",        "D,S,T",        0x4b40000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"add.s",   "D,V,T",   0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
 {"add.d",   "D,V,T",   0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
 {"add.ob",  "X,Y,Q",   0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"add.ob",  "D,S,T",   0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"add.ob",  "D,S,T[e]",        0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"add.ob",  "D,S,k",   0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"add.ps",  "D,V,T",   0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33   },
+{"add.ps",  "D,V,T",   0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33|IL2F      },
+{"add.ps",  "D,V,T",   0x45600000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              IL2E    },
 {"add.qh",  "X,Y,Q",   0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"adda.ob", "Y,Q",     0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
 {"adda.qh", "Y,Q",     0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
@@ -218,6 +225,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"addr.ps", "D,S,T",   0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              M3D     },
 {"addu",    "d,v,t",   0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"addu",    "t,r,I",   0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1      },
+{"addu",       "D,S,T",        0x45800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"addu",       "D,S,T",        0x4b00000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
@@ -226,6 +235,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0,            MX      },
 {"and",     "d,v,t",   0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"and",     "t,r,I",   0,    (int) M_AND_I,    INSN_MACRO,             0,              I1      },
+{"and",        "D,S,T",        0x47c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"and",        "D,S,T",        0x4bc00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"and.ob",  "X,Y,Q",   0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"and.ob",  "D,S,T",   0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"and.ob",  "D,S,T[e]",        0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
@@ -312,13 +323,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.f.d",   "M,S,T",    0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.f.s",   "S,T",      0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.f.s",   "M,S,T",    0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.f.ps",  "S,T",     0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.f.ps",  "S,T",     0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.f.ps",  "S,T",     0x45600030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.f.ps",  "M,S,T",   0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.un.d",  "S,T",     0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.un.d",  "M,S,T",    0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.un.s",  "S,T",      0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.un.s",  "M,S,T",    0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.un.ps", "S,T",     0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.un.ps", "S,T",     0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.un.ps", "S,T",     0x45600031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.un.ps", "M,S,T",   0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.eq.d",  "S,T",     0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.eq.d",  "M,S,T",    0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
@@ -328,62 +341,72 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.eq.ob", "S,T",     0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.eq.ob", "S,T[e]",  0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.eq.ob", "S,k",     0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
-{"c.eq.ps", "S,T",     0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.eq.ps", "S,T",     0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.eq.ps", "S,T",     0x45600032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.eq.ps", "M,S,T",   0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.eq.qh", "Y,Q",     0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
 {"c.ueq.d", "S,T",     0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.ueq.d", "M,S,T",    0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ueq.s", "S,T",      0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.ueq.s", "M,S,T",    0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.ueq.ps","S,T",     0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.ueq.ps","S,T",     0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ueq.ps","S,T",     0x45600033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ueq.ps","M,S,T",   0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.olt.d", "S,T",      0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,             I1      },
 {"c.olt.d", "M,S,T",    0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.olt.s", "S,T",     0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,              I1      },
 {"c.olt.s", "M,S,T",    0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.olt.ps","S,T",     0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.olt.ps","S,T",     0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.olt.ps","S,T",     0x45600034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.olt.ps","M,S,T",   0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.ult.d", "S,T",     0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.ult.d", "M,S,T",    0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ult.s", "S,T",      0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.ult.s", "M,S,T",    0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.ult.ps","S,T",     0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.ult.ps","S,T",     0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ult.ps","S,T",     0x45600035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ult.ps","M,S,T",   0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.ole.d", "S,T",      0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,             I1      },
 {"c.ole.d", "M,S,T",    0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ole.s", "S,T",      0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.ole.s", "M,S,T",    0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.ole.ps","S,T",     0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.ole.ps","S,T",     0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ole.ps","S,T",     0x45600036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ole.ps","M,S,T",   0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.ule.d", "S,T",     0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.ule.d", "M,S,T",    0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ule.s", "S,T",      0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.ule.s", "M,S,T",    0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.ule.ps","S,T",     0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.ule.ps","S,T",     0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ule.ps","S,T",     0x45600037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ule.ps","M,S,T",   0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.sf.d",  "S,T",     0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.sf.d",  "M,S,T",    0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.sf.s",  "S,T",      0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.sf.s",  "M,S,T",    0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.sf.ps", "S,T",     0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.sf.ps", "S,T",     0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.sf.ps", "S,T",     0x45600038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.sf.ps", "M,S,T",   0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.ngle.d","S,T",     0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.ngle.d","M,S,T",    0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ngle.s","S,T",      0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.ngle.s","M,S,T",    0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.ngle.ps","S,T",    0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.ngle.ps","S,T",    0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ngle.ps","S,T",    0x45600039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ngle.ps","M,S,T",  0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.seq.d", "S,T",     0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.seq.d", "M,S,T",    0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.seq.s", "S,T",      0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.seq.s", "M,S,T",    0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.seq.ps","S,T",     0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.seq.ps","S,T",     0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.seq.ps","S,T",     0x4560003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.seq.ps","M,S,T",   0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.ngl.d", "S,T",     0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.ngl.d", "M,S,T",    0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ngl.s", "S,T",      0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.ngl.s", "M,S,T",    0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.ngl.ps","S,T",     0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.ngl.ps","S,T",     0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ngl.ps","S,T",     0x4560003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ngl.ps","M,S,T",   0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.lt.d",  "S,T",     0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.lt.d",  "M,S,T",    0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
@@ -393,14 +416,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.lt.ob", "S,T",     0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.lt.ob", "S,T[e]",  0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.lt.ob", "S,k",     0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
-{"c.lt.ps", "S,T",     0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.lt.ps", "S,T",     0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.lt.ps", "S,T",     0x4560003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.lt.ps", "M,S,T",   0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.lt.qh", "Y,Q",     0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
 {"c.nge.d", "S,T",     0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.nge.d", "M,S,T",    0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.nge.s", "S,T",      0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.nge.s", "M,S,T",    0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.nge.ps","S,T",     0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.nge.ps","S,T",     0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.nge.ps","S,T",     0x4560003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.nge.ps","M,S,T",   0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.le.d",  "S,T",     0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.le.d",  "M,S,T",    0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
@@ -410,14 +435,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"c.le.ob", "S,T",     0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.le.ob", "S,T[e]",  0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T,        0,              N54     },
 {"c.le.ob", "S,k",     0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T,        0,              N54     },
-{"c.le.ps", "S,T",     0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.le.ps", "S,T",     0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.le.ps", "S,T",     0x4560003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.le.ps", "M,S,T",   0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"c.le.qh", "Y,Q",     0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D,   0,              MX      },
 {"c.ngt.d", "S,T",     0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I1      },
 {"c.ngt.d", "M,S,T",    0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,             I4_32   },
 {"c.ngt.s", "S,T",      0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S,   0,             I1      },
 {"c.ngt.s", "M,S,T",    0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S,   0,             I4_32   },
-{"c.ngt.ps","S,T",     0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
+{"c.ngt.ps","S,T",     0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33|IL2F      },
+{"c.ngt.ps","S,T",     0x4560003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D,   0,              IL2E    },
 {"c.ngt.ps","M,S,T",   0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              I5_33   },
 {"cabs.eq.d",  "M,S,T",        0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
 {"cabs.eq.ps", "M,S,T",        0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D,   0,              M3D     },
@@ -514,6 +541,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dabs",    "d,v",     0,    (int) M_DABS,     INSN_MACRO,             0,              I3      },
 {"dadd",    "d,v,t",   0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
 {"dadd",    "t,r,I",   0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3      },
+{"dadd",       "D,S,T",        0x45e00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"dadd",       "D,S,T",        0x4b60000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"daddi",   "t,r,j",   0x60000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
 {"daddiu",  "t,r,j",   0x64000000, 0xfc000000, WR_t|RD_s,              0,              I3      },
 {"daddu",   "d,v,t",   0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
@@ -626,18 +655,26 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsll",    "d,w,s",   0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsllv */
 {"dsll",    "d,w,>",   0x0000003c, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsll32 */
 {"dsll",    "d,w,<",   0x00000038, 0xffe0003f, WR_d|RD_t,              0,              I3      },
+{"dsll",       "D,S,T",        0x45a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"dsll",       "D,S,T",        0x4b20000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"dsrav",   "d,t,s",   0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
 {"dsra32",  "d,w,<",   0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      },
 {"dsra",    "d,w,s",   0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrav */
 {"dsra",    "d,w,>",   0x0000003f, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsra32 */
 {"dsra",    "d,w,<",   0x0000003b, 0xffe0003f, WR_d|RD_t,              0,              I3      },
+{"dsra",       "D,S,T",        0x45e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"dsra",       "D,S,T",        0x4b60000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"dsrlv",   "d,t,s",   0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      },
 {"dsrl32",  "d,w,<",   0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      },
 {"dsrl",    "d,w,s",   0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I3      }, /* dsrlv */
 {"dsrl",    "d,w,>",   0x0000003e, 0xffe0003f, WR_d|RD_t,              0,              I3      }, /* dsrl32 */
 {"dsrl",    "d,w,<",   0x0000003a, 0xffe0003f, WR_d|RD_t,              0,              I3      },
+{"dsrl",       "D,S,T",        0x45a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"dsrl",       "D,S,T",        0x4b20000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"dsub",    "d,v,t",   0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
 {"dsub",    "d,v,I",   0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3      },
+{"dsub",       "D,S,T",        0x45e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"dsub",       "D,S,T",        0x4b60000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"dsubu",   "d,v,t",   0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I3      },
 {"dsubu",   "d,v,I",   0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3      },
 {"dvpe",    "",                0x41600001, 0xffffffff, TRAP,                   0,              MT32    },
@@ -766,8 +803,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mad",     "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             P3      },
 {"madu",    "s,t",      0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             P3      },
 {"madd.d",  "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I4_33   },
+{"madd.d",     "D,S,T",        0x46200018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"madd.d",     "D,S,T",        0x72200018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"madd.s",  "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S,    0,         I4_33   },
+{"madd.s",     "D,S,T",        0x46000018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"madd.s",     "D,S,T",        0x72000018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D,    0,         I5_33   },
+{"madd.ps",    "D,S,T",        0x45600018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"madd.ps",    "D,S,T",        0x71600018,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"madd",    "s,t",      0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO,           0,                L1      },
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO,          0,                I32|N55 },
 {"madd",    "s,t",      0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M,      0,                G1      },
@@ -828,14 +871,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"min.qh",  "X,Y,Q",   0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"mov.d",   "D,S",     0x46200006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
 {"mov.s",   "D,S",     0x46000006, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
-{"mov.ps",  "D,S",     0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33   },
+{"mov.ps",  "D,S",     0x46c00006, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33|IL2F      },
+{"mov.ps",  "D,S",     0x45600006, 0xffff003f, WR_D|RD_S|FP_D,         0,              IL2E    },
 {"movf",    "d,s,N",    0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0,          I4_32  },
 {"movf.d",  "D,S,N",    0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             I4_32   },
 {"movf.l",  "D,S,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
 {"movf.l",  "X,Y,N",   0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              MX|SB1  },
 {"movf.s",  "D,S,N",    0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,             I4_32   },
 {"movf.ps", "D,S,N",   0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5_33   },
-{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              I4_32   },
+{"movn",    "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              I4_32|IL2E|IL2F },
+{"movnz",   "d,v,t",    0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              IL2E|IL2F       },
 {"ffc",     "d,v",     0x0000000b, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
 {"movn.d",  "D,S,t",    0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I4_32   },
 {"movn.l",  "D,S,t",    0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             MX|SB1  },
@@ -848,7 +893,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"movt.l",  "X,Y,N",    0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,             MX|SB1  },
 {"movt.s",  "D,S,N",    0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S,   0,             I4_32   },
 {"movt.ps", "D,S,N",   0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D,   0,              I5_33   },
-{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              I4_32   },
+{"movz",    "d,v,t",    0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t,        0,              I4_32|IL2E|IL2F },
 {"ffs",     "d,v",     0x0000000a, 0xfc1f07ff, WR_d|RD_s,              0,              L1      },
 {"movz.d",  "D,S,t",    0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             I4_32   },
 {"movz.l",  "D,S,t",    0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D,    0,             MX|SB1  },
@@ -862,8 +907,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* move is at the top of the table.  */
 {"msgn.qh", "X,Y,Q",   0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"msub.d",  "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4_33   },
+{"msub.d",     "D,S,T",        0x46200019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"msub.d",     "D,S,T",        0x72200019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"msub.s",  "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4_33   },
+{"msub.s",     "D,S,T",        0x46000019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"msub.s",     "D,S,T",        0x72000019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5_33   },
+{"msub.ps",    "D,S,T",        0x45600019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"msub.ps",    "D,S,T",        0x71600019,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"msub",    "s,t",      0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO,     0,              L1      },
 {"msub",    "s,t",      0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO,     0,             I32|N55 },
 {"msub",    "7,s,t",   0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t,        0,              D33     },
@@ -912,7 +963,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mul.ob",  "D,S,T",   0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"mul.ob",  "D,S,T[e]",        0x48000030, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"mul.ob",  "D,S,k",   0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"mul.ps",  "D,V,T",   0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33   },
+{"mul.ps",  "D,V,T",   0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33|IL2F      },
+{"mul.ps",  "D,V,T",   0x45600002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              IL2E    },
 {"mul.qh",  "X,Y,Q",   0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"mul",     "d,v,t",    0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0,             I32|P3|N55},
 {"mul",     "d,s,t",   0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0,              N54     },
@@ -961,16 +1013,31 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"negu",    "d,w",     0x00000023, 0xffe007ff, WR_d|RD_t,              0,              I1      }, /* subu 0 */
 {"neg.d",   "D,V",     0x46200007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I1      },
 {"neg.s",   "D,V",     0x46000007, 0xffff003f, WR_D|RD_S|FP_S,         0,              I1      },
-{"neg.ps",  "D,V",     0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33   },
+{"neg.ps",  "D,V",     0x46c00007, 0xffff003f, WR_D|RD_S|FP_D,         0,              I5_33|IL2F      },
+{"neg.ps",  "D,V",     0x45600007, 0xffff003f, WR_D|RD_S|FP_D,         0,              IL2E    },
 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4_33   },
+{"nmadd.d",    "D,S,T",        0x4620001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"nmadd.d",    "D,S,T",        0x7220001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4_33   },
+{"nmadd.s",    "D,S,T",        0x4600001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"nmadd.s",    "D,S,T",        0x7200001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5_33   },
+{"nmadd.ps",   "D,S,T",        0x4560001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"nmadd.ps",   "D,S,T",        0x7160001a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I4_33   },
+{"nmsub.d",    "D,S,T",        0x4620001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"nmsub.d",    "D,S,T",        0x7220001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0,            I4_33   },
+{"nmsub.s",    "D,S,T",        0x4600001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"nmsub.s",    "D,S,T",        0x7200001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0,            I5_33   },
+{"nmsub.ps",   "D,S,T",        0x4560001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"nmsub.ps",   "D,S,T",        0x7160001b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 /* nop is at the start of the table.  */
 {"nor",     "d,v,t",   0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"nor",     "t,r,I",   0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1      },
+{"nor",        "D,S,T",        0x47a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"nor",        "D,S,T",        0x4ba00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"nor.ob",  "X,Y,Q",   0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"nor.ob",  "D,S,T",   0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"nor.ob",  "D,S,T[e]",        0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
@@ -979,6 +1046,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"not",     "d,v",     0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t,         0,              I1      },/*nor d,s,0*/
 {"or",      "d,v,t",   0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"or",      "t,r,I",   0,    (int) M_OR_I,     INSN_MACRO,             0,              I1      },
+{"or", "D,S,T",        0x45a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"or", "D,S,T",        0x4b20000c,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"or.ob",   "X,Y,Q",   0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"or.ob",   "D,S,T",   0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"or.ob",   "D,S,T[e]",        0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
@@ -1101,6 +1170,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"selsr",   "d,v,t",   0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              L1      },
 {"seq",     "d,v,t",   0,    (int) M_SEQ,      INSN_MACRO,             0,              I1      },
 {"seq",     "d,v,I",   0,    (int) M_SEQ_I,    INSN_MACRO,             0,              I1      },
+{"seq",        "S,T",          0x46a00032,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"seq",        "S,T",          0x4ba0000c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
 {"sge",     "d,v,t",   0,    (int) M_SGE,      INSN_MACRO,             0,              I1      },
 {"sge",     "d,v,I",   0,    (int) M_SGE_I,    INSN_MACRO,             0,              I1      },
 {"sgeu",    "d,v,t",   0,    (int) M_SGEU,     INSN_MACRO,             0,              I1      },
@@ -1127,21 +1198,31 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0,              MX|SB1  },
 {"sle",     "d,v,t",   0,    (int) M_SLE,      INSN_MACRO,             0,              I1      },
 {"sle",     "d,v,I",   0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1      },
+{"sle",        "S,T",          0x46a0003e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"sle",        "S,T",          0x4ba0000e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
 {"sleu",    "d,v,t",   0,    (int) M_SLEU,     INSN_MACRO,             0,              I1      },
 {"sleu",    "d,v,I",   0,    (int) M_SLEU_I,   INSN_MACRO,             0,              I1      },
+{"sleu",       "S,T",          0x4680003e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"sleu",       "S,T",          0x4b80000e,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
 {"sllv",    "d,t,s",   0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
 {"sll",     "d,w,s",   0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* sllv */
 {"sll",     "d,w,<",   0x00000000, 0xffe0003f, WR_d|RD_t,              0,              I1      },
+{"sll",        "D,S,T",        0x45800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"sll",        "D,S,T",        0x4b00000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"sll.ob",  "X,Y,Q",   0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"sll.ob",  "D,S,T[e]",        0x48000010, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sll.ob",  "D,S,k",   0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sll.qh",  "X,Y,Q",   0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"slt",     "d,v,t",   0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"slt",     "d,v,I",   0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1      },
+{"slt",        "S,T",          0x46a0003c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"slt",        "S,T",          0x4ba0000d,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
 {"slti",    "t,r,j",   0x28000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
 {"sltiu",   "t,r,j",   0x2c000000, 0xfc000000, WR_t|RD_s,              0,              I1      },
 {"sltu",    "d,v,t",   0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"sltu",    "d,v,I",   0,    (int) M_SLTU_I,   INSN_MACRO,             0,              I1      },
+{"sltu",       "S,T",          0x4680003c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"sltu",       "S,T",          0x4b80000d,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
 {"sne",     "d,v,t",   0,    (int) M_SNE,      INSN_MACRO,             0,              I1      },
 {"sne",     "d,v,I",   0,    (int) M_SNE_I,    INSN_MACRO,             0,              I1      },
 {"sqrt.d",  "D,S",     0x46200004, 0xffff003f, WR_D|RD_S|FP_D,         0,              I2      },
@@ -1150,10 +1231,14 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"srav",    "d,t,s",   0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
 {"sra",     "d,w,s",   0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srav */
 {"sra",     "d,w,<",   0x00000003, 0xffe0003f, WR_d|RD_t,              0,              I1      },
+{"sra",        "D,S,T",        0x45c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"sra",        "D,S,T",        0x4b40000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"sra.qh",  "X,Y,Q",   0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"srlv",    "d,t,s",   0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      },
 {"srl",     "d,w,s",   0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s,         0,              I1      }, /* srlv */
 {"srl",     "d,w,<",   0x00000002, 0xffe0003f, WR_d|RD_t,              0,              I1      },
+{"srl",        "D,S,T",        0x45800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"srl",        "D,S,T",        0x4b00000f,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"srl.ob",  "X,Y,Q",   0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"srl.ob",  "D,S,T[e]",        0x48000012, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"srl.ob",  "D,S,k",   0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
@@ -1162,13 +1247,16 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"standby", "",         0x42000021, 0xffffffff,        0,                      0,              V1      },
 {"sub",     "d,v,t",   0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"sub",     "d,v,I",   0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1      },
+{"sub",        "D,S,T",        0x45c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"sub",        "D,S,T",        0x4b40000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"sub.d",   "D,V,T",   0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I1      },
 {"sub.s",   "D,V,T",   0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S,    0,              I1      },
 {"sub.ob",  "X,Y,Q",   0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"sub.ob",  "D,S,T",   0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sub.ob",  "D,S,T[e]",        0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"sub.ob",  "D,S,k",   0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
-{"sub.ps",  "D,V,T",   0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33   },
+{"sub.ps",  "D,V,T",   0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              I5_33|IL2F      },
+{"sub.ps",  "D,V,T",   0x45600001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D,    0,              IL2E    },
 {"sub.qh",  "X,Y,Q",   0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX      },
 {"suba.ob", "Y,Q",     0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX|SB1  },
 {"suba.qh", "Y,Q",     0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
@@ -1176,6 +1264,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"subl.qh", "Y,Q",     0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D,         WR_MACC,        MX      },
 {"subu",    "d,v,t",   0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"subu",    "d,v,I",   0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1      },
+{"subu",       "D,S,T",        0x45800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2E    },
+{"subu",       "D,S,T",        0x4b00000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_S,    0,      IL2F    },
 {"suspend", "",         0x42000022, 0xffffffff,        0,                      0,              V1      },
 {"suxc1",   "S,t(b)",   0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b,     0,              I5_33|N55},
 {"sw",      "t,o(b)",  0xac000000, 0xfc000000, SM|RD_t|RD_b,           0,              I1      },
@@ -1276,6 +1366,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"wsbh",    "d,w",     0x7c0000a0, 0xffe007ff, WR_d|RD_t,              0,              I33     },
 {"xor",     "d,v,t",   0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t,         0,              I1      },
 {"xor",     "t,r,I",   0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1      },
+{"xor",        "D,S,T",        0x47800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"xor",        "D,S,T",        0x4b800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
 {"xor.ob",  "X,Y,Q",   0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D,    0,              MX|SB1  },
 {"xor.ob",  "D,S,T",   0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T,         0,              N54     },
 {"xor.ob",  "D,S,T[e]",        0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T,         0,              N54     },
@@ -1393,18 +1485,6 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtc3",    "t,G",     0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC,   0,              I1      },
 {"mtc3",    "t,G,H",    0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC,   0,             I32     },
 
-/* No hazard protection on coprocessor instructions--they shouldn't
-   change the state of the processor and if they do it's up to the
-   user to put in nops as necessary.  These are at the end so that the
-   disassembler recognizes more specific versions first.  */
-{"c0",      "C",       0x42000000, 0xfe000000, 0,                      0,              I1      },
-{"c1",      "C",       0x46000000, 0xfe000000, 0,                      0,              I1      },
-{"c2",      "C",       0x4a000000, 0xfe000000, 0,                      0,              I1      },
-{"c3",      "C",       0x4e000000, 0xfe000000, 0,                      0,              I1      },
-{"cop0",     "C",      0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
-{"cop1",     "C",      0,    (int) M_COP1,     INSN_MACRO,             0,              I1      },
-{"cop2",     "C",      0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },
-{"cop3",     "C",      0,    (int) M_COP3,     INSN_MACRO,             0,              I1      },
   /* Conflicts with the 4650's "mul" instruction.  Nobody's using the
      4010 any more, so move this insn out of the way.  If the object
      format gave us more info, we could do this right.  */
@@ -1697,6 +1777,161 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"bc0fl",   "p",       0x41020000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
 {"bc0t",    "p",       0x41010000, 0xffff0000, CBD|RD_CC,              0,              I1      },
 {"bc0tl",   "p",       0x41030000, 0xffff0000, CBL|RD_CC,              0,              I2|T3   },
+/* ST Microelectronics Loongson-2E and -2F.  */
+{"mult.g",     "d,s,t",        0x7c000018,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"mult.g",     "d,s,t",        0x70000010,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"multu.g",    "d,s,t",        0x7c000019,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"multu.g",    "d,s,t",        0x70000012,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"dmult.g",    "d,s,t",        0x7c00001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"dmult.g",    "d,s,t",        0x70000011,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"dmultu.g",   "d,s,t",        0x7c00001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"dmultu.g",   "d,s,t",        0x70000013,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"div.g",      "d,s,t",        0x7c00001a,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"div.g",      "d,s,t",        0x70000014,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"divu.g",     "d,s,t",        0x7c00001b,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"divu.g",     "d,s,t",        0x70000016,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"ddiv.g",     "d,s,t",        0x7c00001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"ddiv.g",     "d,s,t",        0x70000015,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"ddivu.g",    "d,s,t",        0x7c00001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"ddivu.g",    "d,s,t",        0x70000017,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"mod.g",      "d,s,t",        0x7c000022,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"mod.g",      "d,s,t",        0x7000001c,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"modu.g",     "d,s,t",        0x7c000023,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"modu.g",     "d,s,t",        0x7000001e,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"dmod.g",     "d,s,t",        0x7c000026,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"dmod.g",     "d,s,t",        0x7000001d,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"dmodu.g",    "d,s,t",        0x7c000027,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2E    },
+{"dmodu.g",    "d,s,t",        0x7000001f,     0xfc0007ff,     RD_s|RD_t|WR_d, 0,      IL2F    },
+{"packsshb",   "D,S,T",        0x47400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"packsshb",   "D,S,T",        0x4b400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"packsswh",   "D,S,T",        0x47200002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"packsswh",   "D,S,T",        0x4b200002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"packushb",   "D,S,T",        0x47600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"packushb",   "D,S,T",        0x4b600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddb",      "D,S,T",        0x47c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddb",      "D,S,T",        0x4bc00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddh",      "D,S,T",        0x47400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddh",      "D,S,T",        0x4b400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddw",      "D,S,T",        0x47600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddw",      "D,S,T",        0x4b600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddd",      "D,S,T",        0x47e00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddd",      "D,S,T",        0x4be00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddsb",     "D,S,T",        0x47800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddsb",     "D,S,T",        0x4b800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddsh",     "D,S,T",        0x47000000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddsh",     "D,S,T",        0x4b000000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddusb",    "D,S,T",        0x47a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddusb",    "D,S,T",        0x4ba00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"paddush",    "D,S,T",        0x47200000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"paddush",    "D,S,T",        0x4b200000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pandn",      "D,S,T",        0x47e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pandn",      "D,S,T",        0x4be00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pavgb",      "D,S,T",        0x46600000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pavgb",      "D,S,T",        0x4b200008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pavgh",      "D,S,T",        0x46400000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pavgh",      "D,S,T",        0x4b000008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpeqb",    "D,S,T",        0x46c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpeqb",    "D,S,T",        0x4b800009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpeqh",    "D,S,T",        0x46800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpeqh",    "D,S,T",        0x4b400009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpeqw",    "D,S,T",        0x46400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpeqw",    "D,S,T",        0x4b000009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpgtb",    "D,S,T",        0x46e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpgtb",    "D,S,T",        0x4ba00009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpgth",    "D,S,T",        0x46a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpgth",    "D,S,T",        0x4b600009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pcmpgtw",    "D,S,T",        0x46600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pcmpgtw",    "D,S,T",        0x4b200009,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pextrh",     "D,S,T",        0x45c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pextrh",     "D,S,T",        0x4b40000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_0",   "D,S,T",        0x47800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pinsrh_0",   "D,S,T",        0x4b800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_1",   "D,S,T",        0x47a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pinsrh_1",   "D,S,T",        0x4ba00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_2",   "D,S,T",        0x47c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pinsrh_2",   "D,S,T",        0x4bc00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pinsrh_3",   "D,S,T",        0x47e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pinsrh_3",   "D,S,T",        0x4be00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmaddhw",    "D,S,T",        0x45e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmaddhw",    "D,S,T",        0x4b60000e,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmaxsh",     "D,S,T",        0x46800000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmaxsh",     "D,S,T",        0x4b400008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmaxub",     "D,S,T",        0x46c00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmaxub",     "D,S,T",        0x4b800008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pminsh",     "D,S,T",        0x46a00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pminsh",     "D,S,T",        0x4b600008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pminub",     "D,S,T",        0x46e00000,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pminub",     "D,S,T",        0x4ba00008,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmovmskb",   "D,S",          0x46a00005,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2E    },
+{"pmovmskb",   "D,S",          0x4ba0000f,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2F    },
+{"pmulhuh",    "D,S,T",        0x46e00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmulhuh",    "D,S,T",        0x4ba0000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmulhh",     "D,S,T",        0x46a00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmulhh",     "D,S,T",        0x4b60000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmullh",     "D,S,T",        0x46800002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmullh",     "D,S,T",        0x4b40000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pmuluw",     "D,S,T",        0x46c00002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pmuluw",     "D,S,T",        0x4b80000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"pasubub",    "D,S,T",        0x45a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pasubub",    "D,S,T",        0x4b20000d,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"biadd",      "D,S",          0x46800005,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2E    },
+{"biadd",      "D,S",          0x4b80000f,     0xffff003f,     RD_S|WR_D|FP_D, 0,      IL2F    },
+{"pshufh",     "D,S,T",        0x47000002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"pshufh",     "D,S,T",        0x4b000002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psllh",      "D,S,T",        0x46600002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psllh",      "D,S,T",        0x4b20000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psllw",      "D,S,T",        0x46400002,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psllw",      "D,S,T",        0x4b00000a,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psrah",      "D,S,T",        0x46a00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psrah",      "D,S,T",        0x4b60000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psraw",      "D,S,T",        0x46800003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psraw",      "D,S,T",        0x4b40000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psrlh",      "D,S,T",        0x46600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psrlh",      "D,S,T",        0x4b20000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psrlw",      "D,S,T",        0x46400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psrlw",      "D,S,T",        0x4b00000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubb",      "D,S,T",        0x47c00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubb",      "D,S,T",        0x4bc00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubh",      "D,S,T",        0x47400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubh",      "D,S,T",        0x4b400001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubw",      "D,S,T",        0x47600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubw",      "D,S,T",        0x4b600001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubd",      "D,S,T",        0x47e00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubd",      "D,S,T",        0x4be00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubsb",     "D,S,T",        0x47800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubsb",     "D,S,T",        0x4b800001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubsh",     "D,S,T",        0x47000001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubsh",     "D,S,T",        0x4b000001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubusb",    "D,S,T",        0x47a00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubusb",    "D,S,T",        0x4ba00001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"psubush",    "D,S,T",        0x47200001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"psubush",    "D,S,T",        0x4b200001,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpckhbh",  "D,S,T",        0x47600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpckhbh",  "D,S,T",        0x4b600003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpckhhw",  "D,S,T",        0x47200003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpckhhw",  "D,S,T",        0x4b200003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpckhwd",  "D,S,T",        0x46e00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpckhwd",  "D,S,T",        0x4ba0000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpcklbh",  "D,S,T",        0x47400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpcklbh",  "D,S,T",        0x4b400003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpcklhw",  "D,S,T",        0x47000003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpcklhw",  "D,S,T",        0x4b000003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"punpcklwd",  "D,S,T",        0x46c00003,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2E    },
+{"punpcklwd",  "D,S,T",        0x4b80000b,     0xffe0003f,     RD_S|RD_T|WR_D|FP_D,    0,      IL2F    },
+{"sequ",       "S,T",          0x46800032,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2E    },
+{"sequ",       "S,T",          0x4b80000c,     0xffe007ff,     RD_S|RD_T|WR_CC|FP_D,   0,      IL2F    },
+/* No hazard protection on coprocessor instructions--they shouldn't
+   change the state of the processor and if they do it's up to the
+   user to put in nops as necessary.  These are at the end so that the
+   disassembler recognizes more specific versions first.  */
+{"c0",      "C",       0x42000000, 0xfe000000, 0,                      0,              I1      },
+{"c1",      "C",       0x46000000, 0xfe000000, 0,                      0,              I1      },
+{"c2",      "C",       0x4a000000, 0xfe000000, 0,                      0,              I1      },
+{"c3",      "C",       0x4e000000, 0xfe000000, 0,                      0,              I1      },
+{"cop0",     "C",      0,    (int) M_COP0,     INSN_MACRO,             0,              I1      },
+{"cop1",     "C",      0,    (int) M_COP1,     INSN_MACRO,             0,              I1      },
+{"cop2",     "C",      0,    (int) M_COP2,     INSN_MACRO,             0,              I1      },
+{"cop3",     "C",      0,    (int) M_COP3,     INSN_MACRO,             0,              I1      }
 };
 
 #define MIPS_NUM_OPCODES \