* @lo: low [31:0] portion of the dma address of TX buffer
* every even is unaligned on 16 bit boundary
* @hi_n_len 0-3 [35:32] portion of dma
- * 4-16 length of the tx buffer
+ * 4-15 length of the tx buffer
*/
struct iwl_tfd_tb {
__le32 lo;
* Transmit Frame Descriptor (TFD)
*
* @ __reserved1[3] reserved
- * @ num_tbs 0-5 number of active tbs
+ * @ num_tbs 0-4 number of active tbs
+ * 5 reserved
* 6-7 padding (not used)
* @ tbs[20] transmit frame buffer descriptors
* @ __pad padding
* Tx frame, up to 8 KBytes in size.
*
* A maximum of 255 (not 256!) TFDs may be on a queue waiting for Tx.
- *
- * Bit fields in the control dword (val0):
*/
struct iwl_tfd {
u8 __reserved1[3];
/* Keep Warm Size */
-#define IWL_KW_SIZE 0x1000 /*4k */
+#define IWL_KW_SIZE 0x1000 /* 4k */
#endif /* !__iwl_fh_h__ */
iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
-
-
/* Alloc and init all Tx queues, including the command queue (#4) */
for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) {
slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
*/
void iwl_txq_ctx_stop(struct iwl_priv *priv)
{
-
int txq_id;
unsigned long flags;
-
/* Turn off all Tx DMA fifos */
spin_lock_irqsave(&priv->lock, flags);
if (iwl_grab_nic_access(priv)) {