[RISCV] Make Zfh PseudoQuietFCMP definitions predicated on HasStdExtZfh

These are currently in a `Predicates = [HasStdExtZfhOrZfhmin]` block,
but Zfhmin has no fcmp instructions so the definition makes no sense for
Zfhmin.

Differential Revision: https://reviews.llvm.org/D146435

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index 43e8fa1dfe0e327e9b10ce0107e1cf50c56ff6c0..3ff445e1397d8e293ab3a8d0ce975c983b54e5c6 100644 (file)
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -206,15 +206,16 @@ def : InstAlias<"fgt.h $rd, $rs, $rt",
                 (FLT_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
 def : InstAlias<"fge.h $rd, $rs, $rt",
                 (FLE_H GPR:$rd, FPR16:$rt, FPR16:$rs), 0>;
-} // Predicates = [HasStdExtZfh]
 
-let Predicates = [HasStdExtZfhOrZfhmin] in {
-def PseudoFLH  : PseudoFloatLoad<"flh", FPR16>;
-def PseudoFSH  : PseudoStore<"fsh", FPR16>;
 let usesCustomInserter = 1 in {
 def PseudoQuietFLE_H : PseudoQuietFCMP<FPR16>;
 def PseudoQuietFLT_H : PseudoQuietFCMP<FPR16>;
 }
+} // Predicates = [HasStdExtZfh]
+
+let Predicates = [HasStdExtZfhOrZfhmin] in {
+def PseudoFLH  : PseudoFloatLoad<"flh", FPR16>;
+def PseudoFSH  : PseudoStore<"fsh", FPR16>;
 } // Predicates = [HasStdExtZfhOrZfhmin]
 
 let Predicates = [HasStdExtZhinx] in {