ehci-mxc: Define host offsets

Some MXC SoCs like the i.MX35 have hosts located at unusual offsets, so prepare
to the introduction of i.MX35 support by defining the ehci-mxc hosts offsets at
SoC level.

Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
Cc: Marek Vasut <marex@denx.de>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 738d411..5f4b543 100644 (file)
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -241,6 +241,7 @@ struct aips_regs {
 #define IMX_RTIC_BASE          (0x53FEC000)
 #define IMX_IIM_BASE           (0x53FF0000)
 #define IMX_USB_BASE           (0x53FF4000)
+#define IMX_USB_PORT_OFFSET    0x200
 #define IMX_CSI_BASE           (0x53FF8000)
 #define IMX_DRYICE_BASE                (0x53FFC000)
 

diff --git a/arch/arm/include/asm/arch-mx31/imx-regs.h b/arch/arm/include/asm/arch-mx31/imx-regs.h
index 01a849d..ae3658b 100644 (file)
--- a/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -895,6 +895,7 @@ struct esdc_regs {
 
 #define MX31_AIPS1_BASE_ADDR   0x43f00000
 #define IMX_USB_BASE           (MX31_AIPS1_BASE_ADDR + 0x88000)
+#define IMX_USB_PORT_OFFSET    0x200
 
 /*
  * CSPI register definitions

diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 846aa3b..6260a8c 100644 (file)
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -169,7 +169,7 @@ int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor)
        udelay(80);
 
        ehci = (struct usb_ehci *)(IMX_USB_BASE +
-               (0x200 * CONFIG_MXC_USB_PORT));
+                       IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
        *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
        *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
                        HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));