Merge tag 'pci-v6.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull pci updates from Bjorn Helgaas:
 "Resource management:

   - Add pci_dev_for_each_resource() and pci_bus_for_each_resource()
     iterators

  PCIe native device hotplug:

   - Fix AB-BA deadlock between reset_lock and device_lock

  Power management:

   - Wait longer for devices to become ready after resume (as we do for
     reset) to accommodate Intel Titan Ridge xHCI devices

   - Extend D3hot delay for NVIDIA HDA controllers to avoid
     unrecoverable devices after a bus reset

  Error handling:

   - Clear PCIe Device Status after EDR since generic error recovery now
     only clears it when AER is native

  ASPM:

   - Work around Chromebook firmware defect that clobbers Capability
     list (including ASPM L1 PM Substates Cap) when returning from
     D3cold to D0

  Freescale i.MX6 PCIe controller driver:

   - Install imprecise external abort handler only when DT indicates
     PCIe support

  Freescale Layerscape PCIe controller driver:

   - Add ls1028a endpoint mode support

  Qualcomm PCIe controller driver:

   - Add SM8550 DT binding and driver support

   - Add SDX55 DT binding and driver support

   - Use bulk APIs for clocks of IP 1.0.0, 2.3.2, 2.3.3

   - Use bulk APIs for reset of IP 2.1.0, 2.3.3, 2.4.0

   - Add DT "mhi" register region for supported SoCs

   - Expose link transition counts via debugfs to help debug low power
     issues

   - Support system suspend and resume; reduce interconnect bandwidth
     and turn off clock and PHY if there are no active devices

   - Enable async probe by default to reduce boot time

  Miscellaneous:

   - Sort controller Kconfig entries by vendor"

* tag 'pci-v6.4-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: (56 commits)
  PCI: xilinx: Drop obsolete dependency on COMPILE_TEST
  PCI: mobiveil: Sort Kconfig entries by vendor
  PCI: dwc: Sort Kconfig entries by vendor
  PCI: Sort controller Kconfig entries by vendor
  PCI: Use consistent controller Kconfig menu entry language
  PCI: xilinx-nwl: Add 'Xilinx' to Kconfig prompt
  PCI: hv: Add 'Microsoft' to Kconfig prompt
  PCI: meson: Add 'Amlogic' to Kconfig prompt
  PCI: Use of_property_present() for testing DT property presence
  PCI/PM: Extend D3hot delay for NVIDIA HDA controllers
  dt-bindings: PCI: qcom: Document msi-map and msi-map-mask properties
  PCI: qcom: Add SM8550 PCIe support
  dt-bindings: PCI: qcom: Add SM8550 compatible
  PCI: qcom: Add support for SDX55 SoC
  dt-bindings: PCI: qcom-ep: Fix the unit address used in example
  dt-bindings: PCI: qcom: Add SDX55 SoC
  dt-bindings: PCI: qcom: Update maintainers entry
  PCI: qcom: Enable async probe by default
  PCI: qcom: Add support for system suspend and resume
  PCI/PM: Drop pci_bridge_wait_for_secondary_bus() timeout parameter
  ...

diff --cc Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml
Simple merge

diff --cc MAINTAINERS
Simple merge

diff --cc arch/arm/mach-mv78xx0/pcie.c
Simple merge

diff --cc arch/x86/pci/fixup.c
index bf5161d,c6c4660..e3ec02e
--- 1/arch/x86/pci/fixup.c
--- 2/arch/x86/pci/fixup.c
+++ b/arch/x86/pci/fixup.c
@@@ -826,22 -825,61 +826,81 @@@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_A
  
  #endif
  
 +#ifdef CONFIG_AMD_NB
 +
 +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2                                  0x10136008
 +#define AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK       0x00000080L
 +
 +static void quirk_clear_strap_no_soft_reset_dev2_f0(struct pci_dev *dev)
 +{
 +      u32 data;
 +
 +      if (!amd_smn_read(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, &data)) {
 +              data &= ~AMD_15B8_RCC_DEV2_EPF0_STRAP2_NO_SOFT_RESET_DEV2_F0_MASK;
 +              if (amd_smn_write(0, AMD_15B8_RCC_DEV2_EPF0_STRAP2, data))
 +                      pci_err(dev, "Failed to write data 0x%x\n", data);
 +      } else {
 +              pci_err(dev, "Failed to read data\n");
 +      }
 +}
 +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15b8, quirk_clear_strap_no_soft_reset_dev2_f0);
 +#endif
++
+ /*
+  * When returning from D3cold to D0, firmware on some Google Coral and Reef
+  * family Chromebooks with Intel Apollo Lake SoC clobbers the headers of
+  * both the L1 PM Substates capability and the previous capability for the
+  * "Celeron N3350/Pentium N4200/Atom E3900 Series PCI Express Port B #1".
+  *
+  * Save those values at enumeration-time and restore them at resume.
+  */
+ 
+ static u16 prev_cap, l1ss_cap;
+ static u32 prev_header, l1ss_header;
+ 
+ static void chromeos_save_apl_pci_l1ss_capability(struct pci_dev *dev)
+ {
+       int pos = PCI_CFG_SPACE_SIZE, prev = 0;
+       u32 header, pheader = 0;
+ 
+       while (pos) {
+               pci_read_config_dword(dev, pos, &header);
+               if (PCI_EXT_CAP_ID(header) == PCI_EXT_CAP_ID_L1SS) {
+                       prev_cap = prev;
+                       prev_header = pheader;
+                       l1ss_cap = pos;
+                       l1ss_header = header;
+                       return;
+               }
+ 
+               prev = pos;
+               pheader = header;
+               pos = PCI_EXT_CAP_NEXT(header);
+       }
+ }
+ 
+ static void chromeos_fixup_apl_pci_l1ss_capability(struct pci_dev *dev)
+ {
+       u32 header;
+ 
+       if (!prev_cap || !prev_header || !l1ss_cap || !l1ss_header)
+               return;
+ 
+       /* Fixup the header of L1SS Capability if missing */
+       pci_read_config_dword(dev, l1ss_cap, &header);
+       if (header != l1ss_header) {
+               pci_write_config_dword(dev, l1ss_cap, l1ss_header);
+               pci_info(dev, "restore L1SS Capability header (was %#010x now %#010x)\n",
+                        header, l1ss_header);
+       }
+ 
+       /* Fixup the link to L1SS Capability if missing */
+       pci_read_config_dword(dev, prev_cap, &header);
+       if (header != prev_header) {
+               pci_write_config_dword(dev, prev_cap, prev_header);
+               pci_info(dev, "restore previous Capability header (was %#010x now %#010x)\n",
+                        header, prev_header);
+       }
+ }
+ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_save_apl_pci_l1ss_capability);
+ DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x5ad6, chromeos_fixup_apl_pci_l1ss_capability);

diff --cc drivers/pci/bus.c
Simple merge

diff --cc drivers/pci/of.c
Simple merge

diff --cc drivers/pci/pci.h
Simple merge

diff --cc drivers/pci/probe.c
Simple merge

diff --cc drivers/pci/remove.c
Simple merge

diff --cc include/linux/pci.h
Simple merge