clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage

1416X/1443X PLL are used on i.MX8MM and i.MX8MN and maybe
other i.MX8M series SoC later, the macro definitions of
these PLLs' initialization should be common for usage.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c
index 6b8e75df994d387d47af89d7d19449aef72a0a16..43fa9c361fcb9021fa095819e1387dbb0d77f901 100644 (file)
--- a/drivers/clk/imx/clk-imx8mm.c
+++ b/drivers/clk/imx/clk-imx8mm.c
@@ -26,23 +26,6 @@ static u32 share_count_dcss;
 static u32 share_count_pdm;
 static u32 share_count_nand;
 
-#define PLL_1416X_RATE(_rate, _m, _p, _s)              \
-       {                                               \
-               .rate   =       (_rate),                \
-               .mdiv   =       (_m),                   \
-               .pdiv   =       (_p),                   \
-               .sdiv   =       (_s),                   \
-       }
-
-#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)          \
-       {                                               \
-               .rate   =       (_rate),                \
-               .mdiv   =       (_m),                   \
-               .pdiv   =       (_p),                   \
-               .sdiv   =       (_s),                   \
-               .kdiv   =       (_k),                   \
-       }
-
 static const struct imx_pll14xx_rate_table imx8mm_pll1416x_tbl[] = {
        PLL_1416X_RATE(1800000000U, 225, 3, 0),
        PLL_1416X_RATE(1600000000U, 200, 3, 0),

diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h
index d94d9cb079d3970e38e0f745d39b8e3311bcb25a..19d7b8b0a00ef97de30162debaae945f66b87b99 100644 (file)
--- a/drivers/clk/imx/clk.h
+++ b/drivers/clk/imx/clk.h
@@ -153,6 +153,23 @@ enum imx_pllv3_type {
 struct clk_hw *imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name,
                const char *parent_name, void __iomem *base, u32 div_mask);
 
+#define PLL_1416X_RATE(_rate, _m, _p, _s)              \
+       {                                               \
+               .rate   =       (_rate),                \
+               .mdiv   =       (_m),                   \
+               .pdiv   =       (_p),                   \
+               .sdiv   =       (_s),                   \
+       }
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k)          \
+       {                                               \
+               .rate   =       (_rate),                \
+               .mdiv   =       (_m),                   \
+               .pdiv   =       (_p),                   \
+               .sdiv   =       (_s),                   \
+               .kdiv   =       (_k),                   \
+       }
+
 struct clk_hw *imx_clk_pllv4(const char *name, const char *parent_name,
                             void __iomem *base);