i965: Make Broadwell HiZ path arrange for TC flushes.

HiZ operations make the depth/render caches out of sync with the sampler
caches.  We need to arrange for a TC flush to happen before the target
buffer is used by the sampler.  Calling brw_render_cache_set_add_bo
makes that happen.

On previous generations, brw_blorp_exec took care of flushing the
texture cache by calling intel_batchbuffer_emit_mi_flush after doing
any rendering.  If we were to use the normal drawing path, then
brw_postdraw_set_buffers_need_resolve would handle this.

On Broadwell, we don't use BLORP, and we don't emit a rectangle
primitive via the normal drawing path.  The 3DSTATE_WM_HZ_OP and
PIPE_CONTROL implicitly make drawing happen.  So, none of our existing
code makes this flush happen - we need to do it directly.

Fixes 11 Piglit copyteximage subtests.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77223
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77226
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>

diff --git a/src/mesa/drivers/dri/i965/gen8_depth_state.c b/src/mesa/drivers/dri/i965/gen8_depth_state.c
index 8f5718a..05c3723 100644 (file)
--- a/src/mesa/drivers/dri/i965/gen8_depth_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_depth_state.c
@@ -307,6 +307,9 @@ gen8_hiz_exec(struct brw_context *brw, struct intel_mipmap_tree *mt,
    OUT_BATCH(0);
    ADVANCE_BATCH();
 
+   /* Mark this buffer as needing a TC flush, as we've rendered to it. */
+   brw_render_cache_set_add_bo(brw, mt->region->bo);
+
    /* We've clobbered all of the depth packets, and the drawing rectangle,
     * so we need to ensure those packets are re-emitted before the next
     * primitive.