board: freescale: p1_p2_rdb_pc: Remove I-flag from second L2 SRAM mapping

U-Boot for initial L2 SRAM uses L2 memory-mapping mode and not L2 with
locked lines. P2020 reference manual about L2 memory-mapping mode says:

  Accesses to memory-mapped SRAM are cacheable only in the corresponding
  e500 L1 caches.

So there is no need to set Caching-Inhibit I-bit for second part of initial
L2 SRAM mapping in TLB entry. Remove it. First part of initial L2 SRAM
mapping already does not have I-bit set.

For more details see also:
https://lore.kernel.org/u-boot/20220508150844.qqxg452rs4wtf5bs@pali/

Signed-off-by: Pali Rohár <pali@kernel.org>

diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 38843a9..105d9e3 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -90,14 +90,14 @@ struct fsl_e_tlb_entry tlb_table[] = {
 #endif /* RAMBOOT/SPL */
 
 #ifdef CONFIG_SYS_INIT_L2_ADDR
-       /* *I*G - L2SRAM */
+       /* ***G - L2SRAM */
        SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
                      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
                      0, 11, BOOKE_PAGESZ_256K, 1),
 #if CONFIG_SYS_L2_SIZE >= (256 << 10)
        SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
                      CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
-                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+                     MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
                      0, 12, BOOKE_PAGESZ_256K, 1)
 #endif
 #endif