COBJS-$(CONFIG_P1020) += ddr-gen3.o
COBJS-$(CONFIG_P2010) += ddr-gen3.o
COBJS-$(CONFIG_P2020) += ddr-gen3.o
+COBJS-$(CONFIG_PPC_P4080) += ddr-gen3.o
COBJS-$(CONFIG_CPM2) += ether_fcc.o
COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
CPU_TYPE_ENTRY(P2010, P2010_E, 1),
CPU_TYPE_ENTRY(P2020, P2020, 2),
CPU_TYPE_ENTRY(P2020, P2020_E, 2),
+ CPU_TYPE_ENTRY(P4040, P4040, 4),
+ CPU_TYPE_ENTRY(P4040, P4040_E, 4),
+ CPU_TYPE_ENTRY(P4080, P4080, 8),
+ CPU_TYPE_ENTRY(P4080, P4080_E, 8),
#elif defined(CONFIG_MPC86xx)
CPU_TYPE_ENTRY(8610, 8610, 1),
CPU_TYPE_ENTRY(8641, 8641, 2),
defined(CONFIG_P1011) || defined(CONFIG_P1020) || \
defined(CONFIG_P2010) || defined(CONFIG_P2020)
#define FSL_HW_NUM_LAWS 12
+#elif defined(CONFIG_PPC_P4080)
+#define FSL_HW_NUM_LAWS 32
#else
#error FSL_HW_NUM_LAWS not defined for this platform
#endif
#if defined(CONFIG_MPC8572) || defined(CONFIG_P1020) || \
defined(CONFIG_P2020) || defined(CONFIG_MPC8641)
-#define CONFIG_MAX_CPUS 2
+#define CONFIG_MAX_CPUS 2
+#elif defined(CONFIG_PPC_P4080)
+#define CONFIG_MAX_CPUS 8
#else
-#define CONFIG_MAX_CPUS 1
+#define CONFIG_MAX_CPUS 1
#endif
#endif /* _ASM_CONFIG_H_ */
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200
#define SVR_P2020_E 0x80EA00
+#define SVR_P4040 0x820100
+#define SVR_P4040_E 0x820900
+#define SVR_P4080 0x820000
+#define SVR_P4080_E 0x820800
#define SVR_8610 0x80A000
#define SVR_8641 0x809000