s5j: tidy up macro definitions of SFR base

Fixes trivial misalignment of macro definitions for better readability
and consistency. In addition, constants that are not in use or
dereferenced are also removed. This commit does not introduce any
functional differences and should not.

Change-Id: I8c3b0f8b51624c722e25e0068664d347da0cac20
Signed-off-by: Heesub Shin <heesub.shin@samsung.com>

diff --git a/os/arch/arm/src/s5j/chip/s5j_memorymap.h b/os/arch/arm/src/s5j/chip/s5j_memorymap.h
index 44c71c5..4a75610 100644 (file)
--- a/os/arch/arm/src/s5j/chip/s5j_memorymap.h
+++ b/os/arch/arm/src/s5j/chip/s5j_memorymap.h
@@ -71,57 +71,48 @@
 #define S5J_PERIPHERAL_SIZE            (256 * 1024 * 1024)
 #define S5J_IRAM_MIRROR_SIZE   (64 * 1024)
 
-#define VECTOR_BASE            0xFFFF0000
+#define VECTOR_BASE                            0xFFFF0000
 
-/* S5J Internal Peripherals at 0x80000000 */
-#define EFUSE_WRITER           0x80000000
-#define CHIPID_BASE                    EFUSE_WRITER
-#define MCT0_BASE                      0x80010000
-#define S5J_TICK_COUNTER       0x80020000
-#define S5J_WDT_BASE           0x80030000
-#define S5J_GPIO_BASE          0x80040000
-#define GPIO_CON_BASE          0x80040000
-
-#define S5J_UARTDBG_BASE       0x80180000
-#define S5J_UART0_BASE         0x80200000
-#define S5J_UART1_BASE         0x80210000
-#define S5J_UART2_BASE         0x80220000
-#define S5J_UART3_BASE         0x80230000
-#define OTP_CON_TOP_BASE       0x100D0000
-#define SDIO_BASE                      0x80300000
-#define SFI_BASE                       0x80310000
-
-#define S5J_GIC_BASE           0x80400000
-#define PMU_BASE                       0x80090000
-#define PMU_ALIVE_BASE         PMU_BASE        /*Temp */
-#define S5J_PWM0_BASE          0x802E0000
-#define S5J_PWM1_BASE          0x802F0000
-#define S5J_SPI0_BASE          0x80240000
-#define S5J_SPI1_BASE          0x80250000
-#define S5J_SPI2_BASE          0x80260000
-#define S5J_SPI3_BASE          0x80270000
-#define S5J_TOP_RTC_BASE       0x80100000
-#define S5J_RTC_BASE           S5J_TOP_RTC_BASE
-#define S5J_PUF_BASE           0x80110000
-#define S5J_CSSYS__BASE                0x801D0000
-#define S5J_CSSYS_CR4_BASE     0x801E0000
-#define S5J_CSSYS_PMU_BASE     0x801F0000
-#define WDT_CPUCL_BASE         S5J_WDT_BASE    /*Temp */
+/* Base Address of SFR at CR4 side */
+#define S5J_CHIPID_BASE                        0x80000000
+#define S5J_MCT_BASE                   0x80010000
+#define S5J_TICK_COUNTER_BASE  0x80020000
+#define S5J_WDT_BASE                   0x80030000
+#define S5J_GPIO_BASE                  0x80040000
 #define S5J_MAILBOX_WIFI_BASE  0x80050000
-#define S5J_MAILBOX_M0_BASE    0x80060000
-#define S5J_CMU_SSS_BASE       0x80070000
-#define S5J_CMU_BASE           0x80080000
-
-#define S5J_SYSREG_BASE                0x800A0000
-#define S5J_PDMA_BASE          0x800B0000
-#define S5J_SSS_SS_BASE                0x800C0000
-#define S5J_SSS_KM_BASE                0x800D0000
-#define S5J_SSS_MB_BASE                0x800E0000
-#define S5J_HSI2C0_BASE                0x80280000
-#define S5J_HSI2C1_BASE                0x80290000
-#define S5J_HSI2C2_BASE                0x802A0000
-#define S5J_HSI2C3_BASE                0x802B0000
-#define S5J_I2S_BASE           0x802C0000
-#define S5J_ADC_BASE           0x802D0000
+#define S5J_MAILBOX_M0_BASE            0x80060000
+#define S5J_CMU_SSS_BASE               0x80070000
+#define S5J_CMU_BASE                   0x80080000
+#define S5J_PMU_BASE                   0x80090000
+#define S5J_SYSREG_BASE                        0x800A0000
+#define S5J_PDMA_BASE                  0x800B0000
+#define S5J_SSS_SS_BASE                        0x800C0000
+#define S5J_SSS_KM_BASE                        0x800D0000
+#define S5J_SSS_MB_BASE                        0x800E0000
+#define S5J_RTC_BASE                   0x80100000
+#define S5J_PUF_BASE                   0x80110000
+#define S5J_UARTDBG_BASE               0x80180000
+#define S5J_CSSYS_BASE                 0x801D0000
+#define S5J_CSSYS_CR4_BASE             0x801E0000
+#define S5J_CSSYS_PMU_BASE             0x801F0000
+#define S5J_UART0_BASE                 0x80200000
+#define S5J_UART1_BASE                 0x80210000
+#define S5J_UART2_BASE                 0x80220000
+#define S5J_UART3_BASE                 0x80230000
+#define S5J_SPI0_BASE                  0x80240000
+#define S5J_SPI1_BASE                  0x80250000
+#define S5J_SPI2_BASE                  0x80260000
+#define S5J_SPI3_BASE                  0x80270000
+#define S5J_HSI2C0_BASE                        0x80280000
+#define S5J_HSI2C1_BASE                        0x80290000
+#define S5J_HSI2C2_BASE                        0x802A0000
+#define S5J_HSI2C3_BASE                        0x802B0000
+#define S5J_I2S_BASE                   0x802C0000
+#define S5J_ADC_BASE                   0x802D0000
+#define S5J_PWM0_BASE                  0x802E0000
+#define S5J_PWM1_BASE                  0x802F0000
+#define S5J_SDIO_BASE                  0x80300000
+#define S5J_SFLASH_BASE                        0x80310000
+#define S5J_GIC_BASE                   0x80400000
 
 #endif /* __ARCH_ARM_SRC_S5J_CHIP_S5J_MEMORYMAP_H */