intel: initialize raw buffer SURFACE_STATEs on view creation

Initialize the SURFACE_STATE for fs once in intel_buf_view_create().  There is
one subtle change: we only use overridden SURFACE_STATEs for raw buffers now.

diff --git a/icd/intel/cmd_pipeline.c b/icd/intel/cmd_pipeline.c
index d130aa6..c90f9ee 100644 (file)
--- a/icd/intel/cmd_pipeline.c
+++ b/icd/intel/cmd_pipeline.c
@@ -1605,39 +1605,20 @@ static uint32_t emit_binding_table(struct intel_cmd *cmd,
                     break;
                 case INTEL_DSET_SLOT_BUF_VIEW:
                     {
-                        XGL_BUFFER_VIEW_CREATE_INFO tmp_info =
-                            dset_slot->u.buf_view->info;
-                        struct intel_buf_view *tmp;
-                        XGL_RESULT res;
-
-                        /* The compiler expects uniform buffers to have pitch of
-                         * 4 for fragment shaders, but 16 for other stages.
-                         */
-                        tmp_info.format.channelFormat = XGL_CH_FMT_R32G32B32A32;
-                        tmp_info.format.numericFormat = XGL_NUM_FMT_FLOAT;
-                        if (XGL_SHADER_STAGE_FRAGMENT == stage) {
-                            tmp_info.stride = 4;
-                        } else {
-                            tmp_info.stride = 16;
-                        }
-
-                        res = intel_buf_view_create(cmd->dev, &tmp_info, &tmp);
-                        if (res != XGL_SUCCESS) {
-                            cmd->result = res;
-                            break;
-                        }
+                        const uint32_t *cmd_data =
+                            (stage != XGL_SHADER_STAGE_FRAGMENT) ?
+                            dset_slot->u.buf_view->cmd :
+                            dset_slot->u.buf_view->fs_cmd;
 
                         offset = cmd_surface_write(cmd, INTEL_CMD_ITEM_SURFACE,
                                 GEN6_ALIGNMENT_SURFACE_STATE,
-                                tmp->cmd_len,
-                                tmp->cmd);
+                                dset_slot->u.buf_view->cmd_len,
+                                cmd_data);
 
                         cmd_reserve_reloc(cmd, 1);
                         cmd_surface_reloc(cmd, offset, 1,
                                 dset_slot->u.buf_view->buf->obj.mem->bo,
-                                tmp->cmd[1], reloc_flags);
-
-                        intel_buf_view_destroy(tmp);
+                                cmd_data[1], reloc_flags);
                     }
                     break;
                 case INTEL_DSET_SLOT_SAMPLER:

diff --git a/icd/intel/view.c b/icd/intel/view.c
index c2c5585..7a2e901 100644 (file)
--- a/icd/intel/view.c
+++ b/icd/intel/view.c
@@ -1070,7 +1070,11 @@ XGL_RESULT intel_buf_view_create(struct intel_dev *dev,
     const bool will_write = (buf->usage |
             (XGL_BUFFER_USAGE_SHADER_ACCESS_WRITE_BIT &
              XGL_BUFFER_USAGE_SHADER_ACCESS_ATOMIC_BIT));
+    XGL_FORMAT format;
+    XGL_GPU_SIZE stride;
+    uint32_t *cmd;
     struct intel_buf_view *view;
+    int i;
 
     view = (struct intel_buf_view *) intel_base_create(dev, sizeof(*view),
             dev->base.dbg, XGL_DBG_OBJECT_BUFFER_VIEW, info, 0);
@@ -1080,18 +1084,43 @@ XGL_RESULT intel_buf_view_create(struct intel_dev *dev,
     view->obj.destroy = buf_view_destroy;
 
     view->buf = buf;
-    view->info = *info;
 
-    if (intel_gpu_gen(dev->gpu) >= INTEL_GEN(7)) {
-        surface_state_buf_gen7(dev->gpu, info->offset,
-                info->range, info->stride, info->format,
-                will_write, will_write, view->cmd);
-        view->cmd_len = 8;
+    /*
+     * The compiler expects uniform buffers to have pitch of
+     * 4 for fragment shaders, but 16 for other stages.  The format
+     * must be XGL_FMT_R32G32B32A32_SFLOAT.
+     */
+    if (info->viewType == XGL_BUFFER_VIEW_RAW) {
+        format.channelFormat = XGL_CH_FMT_R32G32B32A32;
+        format.numericFormat = XGL_NUM_FMT_FLOAT;
+        stride = 16;
     } else {
-        surface_state_buf_gen6(dev->gpu, info->offset,
-                info->range, info->stride, info->format,
-                will_write, will_write, view->cmd);
-        view->cmd_len = 6;
+        format = info->format;
+        stride = info->stride;
+    }
+    cmd = view->cmd;
+
+    for (i = 0; i < 2; i++) {
+        if (intel_gpu_gen(dev->gpu) >= INTEL_GEN(7)) {
+            surface_state_buf_gen7(dev->gpu, info->offset,
+                    info->range, stride, format,
+                    will_write, will_write, cmd);
+            view->cmd_len = 8;
+        } else {
+            surface_state_buf_gen6(dev->gpu, info->offset,
+                    info->range, stride, format,
+                    will_write, will_write, cmd);
+            view->cmd_len = 6;
+        }
+
+        /* switch to view->fs_cmd */
+        if (info->viewType == XGL_BUFFER_VIEW_RAW) {
+            cmd = view->fs_cmd;
+            stride = 4;
+        } else {
+            memcpy(view->fs_cmd, view->cmd, sizeof(uint32_t) * view->cmd_len);
+            break;
+        }
     }
 
     *view_ret = view;

diff --git a/icd/intel/view.h b/icd/intel/view.h
index 04a7693..8956123 100644 (file)
--- a/icd/intel/view.h
+++ b/icd/intel/view.h
@@ -46,10 +46,10 @@ struct intel_buf_view {
     struct intel_obj obj;
 
     struct intel_buf *buf;
-    XGL_BUFFER_VIEW_CREATE_INFO info;
 
     /* SURFACE_STATE */
     uint32_t cmd[8];
+    uint32_t fs_cmd[8];
     XGL_UINT cmd_len;
 };