unsigned mask = nir_ssa_def_components_read(&instr->dest.ssa) << component;
unsigned num_channels = MIN2(util_last_bit(mask), vtx_info->num_channels);
- bool post_shuffle = ctx->options->key.vs.vertex_post_shuffle & (1 << location);
- if (post_shuffle)
- num_channels = MAX2(num_channels, 3);
unsigned desc_index =
ctx->program->info->vs.use_per_attribute_vb_descs ? location : attrib_binding;
bool direct_fetch = false;
/* skip unused channels at the start */
- if (vtx_info->chan_byte_size && !post_shuffle) {
+ if (vtx_info->chan_byte_size) {
channel_start = ffs(mask) - 1;
for (unsigned i = 0; i < MIN2(channel_start, num_channels); i++)
channels[i] = Temp(0, s1);
- } else if (vtx_info->chan_byte_size && post_shuffle && !(mask & 0x8)) {
- num_channels = 3 - (ffs(mask) - 1);
}
/* load channels */
}
Temp fetch_dst;
- if (channel_start == 0 && fetch_bytes == dst.bytes() && !post_shuffle && !expanded &&
+ if (channel_start == 0 && fetch_bytes == dst.bytes() && !expanded &&
num_channels <= 3) {
direct_fetch = true;
fetch_dst = dst;
bool is_float =
nfmt != V_008F0C_BUF_NUM_FORMAT_UINT && nfmt != V_008F0C_BUF_NUM_FORMAT_SINT;
- static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
- static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
- const unsigned* swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
unsigned num_components = instr->dest.ssa.num_components;
aco_ptr<Instruction> vec{create_instruction<Pseudo_instruction>(
unsigned num_temp = 0;
for (unsigned i = 0; i < num_components; i++) {
unsigned idx = i + component;
- if (swizzle[idx] < num_channels && channels[swizzle[idx]].id()) {
- Temp channel = channels[swizzle[idx]];
+ if (idx < num_channels && channels[idx].id()) {
+ Temp channel = channels[idx];
vec->operands[i] = Operand(channel);
num_temp++;
unsigned attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[attrib_index];
unsigned attrib_stride = ctx->options->key.vs.vertex_attribute_strides[attrib_index];
- if (ctx->options->key.vs.vertex_post_shuffle & (1 << attrib_index)) {
- /* Always load, at least, 3 channels for formats that need to be shuffled because X<->Z. */
- num_channels = MAX2(num_channels, 3);
- }
-
unsigned desc_index =
ctx->shader_info->vs.use_per_attribute_vb_descs ? attrib_index : attrib_binding;
desc_index = util_bitcount(ctx->shader_info->vs.vb_desc_usage_mask &
ctx->ac.i32_0, ctx->ac.i32_0, num_channels, data_format, num_format, 0, true);
}
- if (ctx->options->key.vs.vertex_post_shuffle & (1 << attrib_index)) {
- LLVMValueRef c[4];
- c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
- c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
- c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
- c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
-
- input = ac_build_gather_values(&ctx->ac, c, 4);
- }
-
input = radv_fixup_vertex_input_fetches(ctx, input, num_channels, is_float);
for (unsigned chan = 0; chan < 4; chan++) {
unsigned location = nir_intrinsic_base(intrin) - VERT_ATTRIB_GENERIC0;
enum radv_vs_input_alpha_adjust alpha_adjust = pipeline_key->vs.vertex_alpha_adjust[location];
+ bool post_shuffle = pipeline_key->vs.vertex_post_shuffle & (1 << location);
- if (alpha_adjust == ALPHA_ADJUST_NONE)
+ if (alpha_adjust == ALPHA_ADJUST_NONE && !post_shuffle)
continue;
unsigned component = nir_intrinsic_component(intrin);
unsigned num_components = intrin->dest.ssa.num_components;
+ static const unsigned swizzle_normal[4] = {0, 1, 2, 3};
+ static const unsigned swizzle_post_shuffle[4] = {2, 1, 0, 3};
+ const unsigned *swizzle = post_shuffle ? swizzle_post_shuffle : swizzle_normal;
+
b.cursor = nir_after_instr(instr);
+ nir_ssa_def *channels[4];
+
+ if (post_shuffle) {
+ /* Expand to load 3 components because it's shuffled like X<->Z. */
+ intrin->num_components = MAX2(component + num_components, 3);
+ intrin->dest.ssa.num_components = intrin->num_components;
+
+ nir_intrinsic_set_component(intrin, 0);
+ }
+
+ for (uint32_t i = 0; i < num_components; i++) {
+ unsigned idx = i + (post_shuffle ? component : 0);
- if (component + num_components == 4) {
+ channels[i] = nir_channel(&b, &intrin->dest.ssa, swizzle[idx]);
+ }
+
+ if (alpha_adjust != ALPHA_ADJUST_NONE && component + num_components == 4) {
unsigned idx = num_components - 1;
- nir_ssa_def *alpha = radv_adjust_vertex_fetch_alpha(
- &b, alpha_adjust, nir_channel(&b, &intrin->dest.ssa, idx));
- nir_ssa_def *new_dest = nir_vector_insert_imm(&b, &intrin->dest.ssa, alpha, idx);
- nir_ssa_def_rewrite_uses_after(&intrin->dest.ssa, new_dest,
- new_dest->parent_instr);
- progress = true;
+ channels[idx] = radv_adjust_vertex_fetch_alpha(&b, alpha_adjust, channels[idx]);
}
+
+ nir_ssa_def *new_dest = nir_vec(&b, channels, num_components);
+
+ nir_ssa_def_rewrite_uses_after(&intrin->dest.ssa, new_dest,
+ new_dest->parent_instr);
+
+ progress = true;
}
}