drm/amdgpu: Fix bug in reporting voltage for CIK

On my R9 390, the voltage was reported as a constant 1000 mV.
This was due to a bug in smu7_hwmgr.c, in the smu7_read_sensor()
function, where some magic constants were used in a condition,
to determine whether the voltage should be read from PLANE2_VID
or PLANE1_VID. The VDDC mask was incorrectly used, instead of
the VDDGFX mask.

This patch changes the code to use the correct defined constants
(and apply the correct bitshift), thus resulting in correct voltage reporting.

Signed-off-by: Sandeep Raghuraman <sandy.8925@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
index ffe05b7cc1f0ae0a566c389443a94b20b7178cae..4a3b64aa21ceb12dc63877954f9994845bbdbba1 100644 (file)
--- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
+++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
@@ -3581,7 +3581,8 @@ static int smu7_read_sensor(struct pp_hwmgr *hwmgr, int idx,
        case AMDGPU_PP_SENSOR_GPU_POWER:
                return smu7_get_gpu_power(hwmgr, (uint32_t *)value);
        case AMDGPU_PP_SENSOR_VDDGFX:
-               if ((data->vr_config & 0xff) == 0x2)
+               if ((data->vr_config & VRCONF_VDDGFX_MASK) ==
+                   (VR_SVI2_PLANE_2 << VRCONF_VDDGFX_SHIFT))
                        val_vid = PHM_READ_INDIRECT_FIELD(hwmgr->device,
                                        CGS_IND_REG__SMC, PWR_SVI2_STATUS, PLANE2_VID);
                else