drm/amdgpu: stop using sratch_reg in IB test

scratch_reg0 is used by RLCG for register access usage
in SRIOV case.

both CP firmware and driver can invoke RLCG to do
certain register access (through scratch_reg0/1/2/3)
but rlcg now dosen't have race concern so if two
clients are in parallel doing the RLCG reg access
then we are colliding,

GFX IB test is a runtime work, so it is forbidden
to use scrach_reg0/1/2/3 during IB test period

note:
Although we can only have this change for SRIOV, but
looks it doesn't worth the effort to differentiate
bare-metal with SRIOV on the GFX ib test

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 74c616ebfc84e92c209cb50ab7b9d98e838e7bb9..3f997aa469076ec65403f75c4c9671fe9ffa3839 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -500,29 +500,28 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
        struct amdgpu_device *adev = ring->adev;
        struct amdgpu_ib ib;
        struct dma_fence *f = NULL;
-       uint32_t scratch;
-       uint32_t tmp = 0;
+       unsigned index;
+       uint64_t gpu_addr;
+       uint32_t tmp;
        long r;
 
-       r = amdgpu_gfx_scratch_get(adev, &scratch);
-       if (r) {
-               DRM_ERROR("amdgpu: failed to get scratch reg (%ld).\n", r);
+       r = amdgpu_device_wb_get(adev, &index);
+       if (r)
                return r;
-       }
-
-       WREG32(scratch, 0xCAFEDEAD);
 
+       gpu_addr = adev->wb.gpu_addr + (index * 4);
+       adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
        memset(&ib, 0, sizeof(ib));
-       r = amdgpu_ib_get(adev, NULL, 256, &ib);
-       if (r) {
-               DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
+       r = amdgpu_ib_get(adev, NULL, 16, &ib);
+       if (r)
                goto err1;
-       }
 
-       ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
-       ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START));
-       ib.ptr[2] = 0xDEADBEEF;
-       ib.length_dw = 3;
+       ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
+       ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+       ib.ptr[2] = lower_32_bits(gpu_addr);
+       ib.ptr[3] = upper_32_bits(gpu_addr);
+       ib.ptr[4] = 0xDEADBEEF;
+       ib.length_dw = 5;
 
        r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
        if (r)
@@ -530,15 +529,13 @@ static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 
        r = dma_fence_wait_timeout(f, false, timeout);
        if (r == 0) {
-               DRM_ERROR("amdgpu: IB test timed out.\n");
                r = -ETIMEDOUT;
                goto err2;
        } else if (r < 0) {
-               DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
                goto err2;
        }
 
-       tmp = RREG32(scratch);
+       tmp = adev->wb.wb[index];
        if (tmp == 0xDEADBEEF)
                r = 0;
        else
@@ -547,8 +544,7 @@ err2:
        amdgpu_ib_free(adev, &ib, NULL);
        dma_fence_put(f);
 err1:
-       amdgpu_gfx_scratch_free(adev, scratch);
-
+       amdgpu_device_wb_free(adev, index);
        return r;
 }