+++ /dev/null
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB = $(obj)lib$(BOARD).o
-
-COBJS-y += $(BOARD).o
-COBJS-y += law.o
-COBJS-y += tlb.o
-COBJS-y += flash.o
-COBJS-$(CONFIG_FSL_DDR1) += ddr.o
-
-SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS := $(addprefix $(obj),$(COBJS-y))
-SOBJS := $(addprefix $(obj),$(SOBJS))
-
-$(LIB): $(obj).depend $(OBJS) $(SOBJS)
- $(call cmd_link_o_target, $(OBJS))
-
-clean:
- rm -f $(OBJS) $(SOBJS)
-
-distclean: clean
- rm -f $(LIB) core *.bak $(obj).depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * Version 2 as published by the Free Software Foundation.
- */
-
-#include <common.h>
-#include <i2c.h>
-
-#include <asm/fsl_ddr_sdram.h>
-#include <asm/fsl_ddr_dimm_params.h>
-
-static void
-get_spd(ddr1_spd_eeprom_t *spd, unsigned char i2c_address)
-{
- i2c_read(i2c_address, 0, 1, (uchar *)spd, sizeof(ddr1_spd_eeprom_t));
-}
-
-
-unsigned int
-fsl_ddr_get_mem_data_rate(void)
-{
- return get_ddr_freq(0);
-}
-
-
-void
-fsl_ddr_get_spd(ddr1_spd_eeprom_t *ctrl_dimms_spd,
- unsigned int ctrl_num)
-{
- unsigned int i;
- unsigned int i2c_address = 0;
-
- for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
- if (ctrl_num == 0 && i == 0) {
- i2c_address = SPD_EEPROM_ADDRESS;
- }
- get_spd(&(ctrl_dimms_spd[i]), i2c_address);
- }
-}
-
-void fsl_ddr_board_options(memctl_options_t *popts,
- dimm_params_t *pdimm,
- unsigned int ctrl_num)
-{
- /*
- * Factors to consider for CPO:
- * - frequency
- * - ddr1 vs. ddr2
- */
- popts->cpo_override = 0;
-
- /*
- * Factors to consider for write data delay:
- * - number of DIMMs
- *
- * 1 = 1/4 clock delay
- * 2 = 1/2 clock delay
- * 3 = 3/4 clock delay
- * 4 = 1 clock delay
- * 5 = 5/4 clock delay
- * 6 = 3/2 clock delay
- */
- popts->write_data_delay = 3;
-
- /*
- * Factors to consider for half-strength driver enable:
- * - number of DIMMs installed
- */
- popts->half_strength_driver_enable = 0;
-}
+++ /dev/null
-/*
- * (C) Copyright 2003 Motorola Inc.
- * Xianghua Xiao,(X.Xiao@motorola.com)
- *
- * (C) Copyright 2000, 2001
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * (C) Copyright 2001, Stuart Hughes, Lineo Inc, stuarth@lineo.com
- * Add support the Sharp chips on the mpc8260ads.
- * I started with board/ip860/flash.c and made changes I found in
- * the MTD project by David Schleef.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-
-#if !defined(CONFIG_SYS_NO_FLASH)
-
-flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-
-#if defined(CONFIG_ENV_IS_IN_FLASH)
-# ifndef CONFIG_ENV_ADDR
-# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
-# endif
-# ifndef CONFIG_ENV_SIZE
-# define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
-# endif
-# ifndef CONFIG_ENV_SECT_SIZE
-# define CONFIG_ENV_SECT_SIZE CONFIG_ENV_SIZE
-# endif
-#endif
-
-/*
- * The variable should be in the flash info structure. Since it
- * is only used in this board specific file it is declared here.
- * In the future I think an endian flag should be part of the
- * flash_info_t structure. (Ron Alder)
- */
-static ulong big_endian = 0;
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info);
-static int write_block (flash_info_t *info, uchar * src, ulong dest, ulong cnt);
-static int write_short (flash_info_t *info, ulong dest, ushort data);
-static int write_word (flash_info_t *info, ulong dest, ulong data);
-static int clear_block_lock_bit(flash_info_t *info, vu_long * addr);
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size;
- int i;
-
- /* Init: enable write,
- * or we cannot even write flash commands
- */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
-
- /* set the default sector offset */
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size, size<<20);
- }
-
- /* Re-do sizing to get full correct info */
- size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
-
- flash_info[0].size = size;
-
-#if !defined(CONFIG_RAM_AS_FLASH)
-#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
- /* monitor protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_SYS_MONITOR_BASE,
- CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
- &flash_info[0]);
-#endif
-
-#ifdef CONFIG_ENV_IS_IN_FLASH
- /* ENV protection ON by default */
- flash_protect(FLAG_PROTECT_SET,
- CONFIG_ENV_ADDR,
- CONFIG_ENV_ADDR+CONFIG_ENV_SECT_SIZE-1,
- &flash_info[0]);
-#endif
-#endif
- return (size);
-}
-
-/*-----------------------------------------------------------------------
- */
-void flash_print_info (flash_info_t *info)
-{
- int i;
-
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("missing or unknown FLASH type\n");
- return;
- }
-
- switch (info->flash_id & FLASH_VENDMASK) {
- case FLASH_MAN_INTEL: printf ("Intel "); break;
- case FLASH_MAN_SHARP: printf ("Sharp "); break;
- default: printf ("Unknown Vendor "); break;
- }
-
- switch (info->flash_id & FLASH_TYPEMASK) {
- case FLASH_28F016SV: printf ("28F016SV (16 Mbit, 32 x 64k)\n");
- break;
- case FLASH_28F160S3: printf ("28F160S3 (16 Mbit, 32 x 512K)\n");
- break;
- case FLASH_28F320S3: printf ("28F320S3 (32 Mbit, 64 x 512K)\n");
- break;
- case FLASH_LH28F016SCT: printf ("28F016SC (16 Mbit, 32 x 64K)\n");
- break;
- case FLASH_28F640J3A: printf ("28F640J3A (64 Mbit, 64 x 128K)\n");
- break;
- default: printf ("Unknown Chip Type\n");
- break;
- }
-
- printf (" Size: %ld MB in %d Sectors\n",
- info->size >> 20, info->sector_count);
-
- printf (" Sector Start Addresses:");
- for (i=0; i<info->sector_count; ++i) {
- if ((i % 5) == 0)
- printf ("\n ");
- printf (" %08lX%s",
- info->start[i],
- info->protect[i] ? " (RO)" : " "
- );
- }
- printf ("\n");
-}
-
- /* only deal with 16 bit and 32 bit port width, 16bit chip */
-static ulong flash_get_size (vu_long *addr, flash_info_t *info)
-{
- short i;
- ulong value,va,vb,vc,vd;
- ulong base = (ulong)addr;
- ulong sector_offset;
-
-#ifdef DEBUG
- printf("Check flash at 0x%08x\n",(uint)addr);
-#endif
- /* Write "Intelligent Identifier" command: read Manufacturer ID */
- *addr = 0x90909090;
- udelay(20);
- asm("sync");
-
-#ifndef CONFIG_SYS_FLASH_CFI
- printf("Not define CONFIG_SYS_FLASH_CFI\n");
- return (0);
-#else
- value = addr[0];
- va=(value & 0xFF000000)>>24;
- vb=(value & 0x00FF0000)>>16;
- vc=(value & 0x0000FF00)>>8;
- vd=(value & 0x000000FF);
- if ((va==0) && (vb==0)) {
- printf("cannot identify Flash\n");
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
- else if ((va==0) && (vb!=0)) {
- big_endian = 1;
- info->chipwidth = FLASH_CFI_BY16;
- if(vb == vd) info->portwidth = FLASH_CFI_32BIT;
- else info->portwidth = FLASH_CFI_16BIT;
- }
- else if ((va!=0) && (vb==0)) {
- big_endian = 0;
- info->chipwidth = FLASH_CFI_BY16;
- if(va == vc) info->portwidth = FLASH_CFI_32BIT;
- else info->portwidth = FLASH_CFI_16BIT;
- }
- else if ((va!=0) && (vb!=0)) {
- big_endian = 1; /* no meaning for 8bit chip */
- info->chipwidth = FLASH_CFI_BY8;
- if(va == vb) info->portwidth = FLASH_CFI_16BIT;
- else info->portwidth = FLASH_CFI_8BIT;
- }
-#ifdef DEBUG
- switch (info->portwidth) {
- case FLASH_CFI_8BIT:
- printf("port width is 8 bit.\n");
- break;
- case FLASH_CFI_16BIT:
- printf("port width is 16 bit, ");
- break;
- case FLASH_CFI_32BIT:
- printf("port width is 32 bit, ");
- break;
- }
- switch (info->chipwidth) {
- case FLASH_CFI_BY16:
- printf("chip width is 16 bit, ");
- switch (big_endian) {
- case 0:
- printf("Little Endian.\n");
- break;
- case 1:
- printf("Big Endian.\n");
- break;
- }
- break;
- }
-#endif
-#endif /*#ifdef CONFIG_SYS_FLASH_CFI*/
-
- if (big_endian==0) value = (addr[0] & 0xFF000000) >>8;
- else value = (addr[0] & 0x00FF0000);
-#ifdef DEBUG
- printf("manufacturer=0x%x\n",(uint)(value>>16));
-#endif
- switch (value) {
- case MT_MANUFACT & 0xFFFF0000: /* SHARP, MT or => Intel */
- case INTEL_ALT_MANU & 0xFFFF0000:
- info->flash_id = FLASH_MAN_INTEL;
- break;
- default:
- printf("unknown manufacturer: %x\n", (unsigned int)value);
- info->flash_id = FLASH_UNKNOWN;
- info->sector_count = 0;
- info->size = 0;
- return (0); /* no or unknown flash */
- }
-
- if (info->portwidth==FLASH_CFI_16BIT) {
- switch (big_endian) {
- case 0:
- value = (addr[0] & 0x0000FF00)>>8;
- break;
- case 1:
- value = (addr[0] & 0x000000FF);
- break;
- }
- }
- else if (info->portwidth == FLASH_CFI_32BIT) {
- switch (big_endian) {
- case 0:
- value = (addr[1] & 0x0000FF00)>>8;
- break;
- case 1:
- value = (addr[1] & 0x000000FF);
- break;
- }
- }
-
-#ifdef DEBUG
- printf("deviceID=0x%x\n",(uint)value);
-#endif
- switch (value) {
- case (INTEL_ID_28F016S & 0x0000FFFF):
- info->flash_id += FLASH_28F016SV;
- info->sector_count = 32;
- sector_offset = 0x10000;
- break; /* => 2 MB */
-
- case (INTEL_ID_28F160S3 & 0x0000FFFF):
- info->flash_id += FLASH_28F160S3;
- info->sector_count = 32;
- sector_offset = 0x10000;
- break; /* => 2 MB */
-
- case (INTEL_ID_28F320S3 & 0x0000FFFF):
- info->flash_id += FLASH_28F320S3;
- info->sector_count = 64;
- sector_offset = 0x10000;
- break; /* => 4 MB */
-
- case (INTEL_ID_28F640J3A & 0x0000FFFF):
- info->flash_id += FLASH_28F640J3A;
- info->sector_count = 64;
- sector_offset = 0x20000;
- break; /* => 8 MB */
-
- case SHARP_ID_28F016SCL & 0x0000FFFF:
- case SHARP_ID_28F016SCZ & 0x0000FFFF:
- info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
- info->sector_count = 32;
- sector_offset = 0x10000;
- break; /* => 2 MB */
-
-
- default:
- info->flash_id = FLASH_UNKNOWN;
- return (0); /* => no or unknown flash */
-
- }
-
- sector_offset = sector_offset * (info->portwidth / info->chipwidth);
- info->size = info->sector_count * sector_offset;
-
- /* set up sector start address table */
- for (i = 0; i < info->sector_count; i++) {
- info->start[i] = base;
- base += sector_offset;
- /* don't know how to check sector protection */
- info->protect[i] = 0;
- }
-
- /*
- * Prevent writes to uninitialized FLASH.
- */
- if (info->flash_id != FLASH_UNKNOWN) {
- addr = (vu_long *)info->start[0];
- *addr = 0xFFFFFF; /* reset bank to read array mode */
- asm("sync");
- }
-
- return (info->size);
-}
-
-
-/*-----------------------------------------------------------------------
- */
-
-int flash_erase (flash_info_t *info, int s_first, int s_last)
-{
- int flag, prot, sect;
- ulong start, now, last, ready, erase_err_status;
-
- if (big_endian == 1) {
- ready = 0x0080;
- erase_err_status = 0x00a0;
- }
- else {
- ready = 0x8000;
- erase_err_status = 0xa000;
- }
- if ((info->portwidth / info->chipwidth)==2) {
- ready += (ready <<16);
- erase_err_status += (erase_err_status <<16);
- }
-
-#ifdef DEBUG
- printf ("\nReady flag is 0x%lx\nErase error flag is 0x%lx", ready, erase_err_status);
-#endif
-
- if ((s_first < 0) || (s_first > s_last)) {
- if (info->flash_id == FLASH_UNKNOWN) {
- printf ("- missing\n");
- } else {
- printf ("- no sectors to erase\n");
- }
- return 1;
- }
-
- if ( ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_INTEL)
- && ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_SHARP) ) {
- printf ("Can't erase unknown flash type %08lx - aborted\n",
- info->flash_id);
- return 1;
- }
-
- prot = 0;
- for (sect=s_first; sect<=s_last; ++sect) {
- if (info->protect[sect]) {
- prot++;
- }
- }
-
- if (prot) {
- printf ("- Warning: %d protected sectors will not be erased!\n",
- prot);
- } else {
- printf ("\n");
- }
-
-#ifdef DEBUG
- printf("\nFlash Erase:\n");
-#endif
- /* Make Sure Block Lock Bit is not set. */
- if(clear_block_lock_bit(info, (vu_long *)(info->start[s_first]))){
- return 1;
- }
-
- /* Start erase on unprotected sectors */
-#if defined(DEBUG)
- printf("Begin to erase now,s_first=0x%x s_last=0x%x...\n",s_first,s_last);
-#endif
- for (sect = s_first; sect<=s_last; sect++) {
- if (info->protect[sect] == 0) { /* not protected */
- vu_short *addr16 = (vu_short *)(info->start[sect]);
- vu_long *addr = (vu_long *)(info->start[sect]);
- printf(".");
- switch (info->portwidth) {
- case FLASH_CFI_16BIT:
- asm("sync");
- last = start = get_timer (0);
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
- /* Reset Array */
- *addr16 = 0xffff;
- asm("sync");
- /* Clear Status Register */
- *addr16 = 0x5050;
- asm("sync");
- /* Single Block Erase Command */
- *addr16 = 0x2020;
- asm("sync");
- /* Confirm */
- *addr16 = 0xD0D0;
- asm("sync");
- if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
- /* Resume Command, as per errata update */
- *addr16 = 0xD0D0;
- asm("sync");
- }
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
- /* wait at least 80us - let's wait 1 ms */
- *addr16 = 0x7070;
- udelay (1000);
- while ((*addr16 & ready) != ready) {
- if((*addr16 & erase_err_status)== erase_err_status){
- printf("Error in Block Erase - Lock Bit may be set!\n");
- printf("Status Register = 0x%X\n", (uint)*addr16);
- *addr16 = 0xFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr16 = 0xFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- /* reset to read mode */
- *addr16 = 0xFFFF;
- asm("sync");
- break;
- case FLASH_CFI_32BIT:
- asm("sync");
- last = start = get_timer (0);
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
- /* Reset Array */
- *addr = 0xffffffff;
- asm("sync");
- /* Clear Status Register */
- *addr = 0x50505050;
- asm("sync");
- /* Single Block Erase Command */
- *addr = 0x20202020;
- asm("sync");
- /* Confirm */
- *addr = 0xD0D0D0D0;
- asm("sync");
- if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
- /* Resume Command, as per errata update */
- *addr = 0xD0D0D0D0;
- asm("sync");
- }
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
- /* wait at least 80us - let's wait 1 ms */
- *addr = 0x70707070;
- udelay (1000);
- while ((*addr & ready) != ready) {
- if((*addr & erase_err_status)==erase_err_status){
- printf("Error in Block Erase - Lock Bit may be set!\n");
- printf("Status Register = 0x%X\n", (uint)*addr);
- *addr = 0xFFFFFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- /* show that we're waiting */
- if ((now - last) > 1000) { /* every second */
- putc ('.');
- last = now;
- }
- }
- /* reset to read mode */
- *addr = 0xFFFFFFFF;
- asm("sync");
- break;
- } /* end switch */
- } /* end if */
- } /* end for */
-
- printf ("flash erase done\n");
- return 0;
-}
-
-/*-----------------------------------------------------------------------
- * Copy memory to flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-
-#define FLASH_BLOCK_SIZE 32
-
-int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
-{
- ulong cp, wp, data, count, temp;
-/* ulong temp[FLASH_BLOCK_SIZE/4];*/
- int i, l, rc;
-
- count = cnt;
- wp = (addr & ~3); /* get lower word aligned address */
-
- /*
- * handle unaligned start bytes
- */
- if ((l = addr - wp) != 0) {
- data = 0;
- for (i=0, cp=wp; i<l; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
- for (; i<4 && cnt>0; ++i) {
- data = (data << 8) | *src++;
- --cnt;
- ++cp;
- }
- for (; cnt==0 && i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- }
-
- cp = wp;
- /* handle unaligned block bytes , flash block size = 16bytes */
- wp = (cp+FLASH_BLOCK_SIZE-1) & ~(FLASH_BLOCK_SIZE-1);
- if ((wp-cp)>=cnt) {
- if ((rc = write_block(info,src,cp,wp-cp)) !=0)
- return (rc);
- src += wp-cp;
- cnt -= wp-cp;
- }
- /* handle aligned block bytes */
- temp = 0;
- printf("\n");
- while ( cnt >= FLASH_BLOCK_SIZE) {
- if ((rc = write_block(info,src,cp,FLASH_BLOCK_SIZE)) !=0) {
- return (rc);
- }
- src += FLASH_BLOCK_SIZE;
- cp += FLASH_BLOCK_SIZE;
- cnt -= FLASH_BLOCK_SIZE;
- if (((count-cnt)>>10)>temp) {
- temp=(count-cnt)>>10;
- printf("\r%lu KB",temp);
- }
- }
- printf("\n");
- wp = cp;
- /*
- * handle word aligned part
- */
- while (cnt >= 4) {
- data = 0;
- for (i=0; i<4; ++i) {
- data = (data << 8) | *src++;
- }
- if ((rc = write_word(info, wp, data)) != 0) {
- return (rc);
- }
- wp += 4;
- cnt -= 4;
- }
-
- if (cnt == 0) {
- return (0);
- }
-
- /*
- * handle unaligned tail bytes
- */
- data = 0;
- for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) {
- data = (data << 8) | *src++;
- --cnt;
- }
- for (; i<4; ++i, ++cp) {
- data = (data << 8) | (*(uchar *)cp);
- }
-
- return (write_word(info, wp, data));
-}
-#undef FLASH_BLOCK_SIZE
-
-/*-----------------------------------------------------------------------
- * Write block to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- * -1 Error
- */
-static int write_block(flash_info_t *info, uchar * src, ulong dest, ulong cnt)
-{
- vu_short *baddr, *addr = (vu_short *)dest;
- ushort data;
- ulong start, now, xsr,csr, ready;
- int flag;
-
- if (cnt==0) return 0;
- else if(cnt != (cnt& ~1)) return -1;
-
- /* Check if Flash is (sufficiently) erased */
- data = * src;
- data = (data<<8) | *(src+1);
- if ((*addr & data) != data) {
- return (2);
- }
- if (big_endian == 1) {
- ready = 0x0080;
- }
- else {
- ready = 0x8000;
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- do {
- /* Write Command */
- *addr = 0xe8e8;
- asm("sync");
- xsr = *addr;
- asm("sync");
- } while (!(xsr & ready)); /*wait until read */
- /*write count=BLOCK SIZE -1 */
- data=(cnt>>1)-1;
- data=(data<<8)|data;
- *addr = data; /* word mode, cnt/2 */
- asm("sync");
- baddr = addr;
- while(cnt) {
- data = * src++;
- data = (data<<8) | *src++;
- asm("sync");
- *baddr = data;
- asm("sync");
- ++baddr;
- cnt = cnt -2;
- }
- *addr = 0xd0d0; /* confirm write */
- start = get_timer(0);
- asm("sync");
- if (flag)
- enable_interrupts();
- /* data polling for D7 */
- flag = 0;
- while (((csr = *addr) & ready) != ready) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- flag = 1;
- break;
- }
- }
- if (csr & 0x4040) {
- printf ("CSR indicates write error (%04lx) at %08lx\n",
- csr, (ulong)addr);
- flag = 1;
- }
- /* Clear Status Registers Command */
- *addr = 0x5050;
- asm("sync");
- /* Reset to read array mode */
- *addr = 0xFFFF;
- asm("sync");
- return (flag);
-}
-
-
-/*-----------------------------------------------------------------------
- * Write a short word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_short (flash_info_t *info, ulong dest, ushort data)
-{
- vu_short *addr = (vu_short *)dest;
- ulong start, now, csr, ready;
- int flag;
-
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- /* Write Command */
- *addr = 0x1010;
- start = get_timer (0);
- asm("sync");
- /* Write Data */
- *addr = data;
- asm("sync");
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
- if (big_endian == 1) {
- ready = 0x0080;
- }
- else {
- ready = 0x8000;
- }
- /* data polling for D7 */
- flag = 0;
- while (((csr = *addr) & ready) != ready) {
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- flag = 1;
- break;
- }
- }
- if (csr & 0x4040) {
- printf ("CSR indicates write error (%04lx) at %08lx\n",
- csr, (ulong)addr);
- flag = 1;
- }
- /* Clear Status Registers Command */
- *addr = 0x5050;
- asm("sync");
- /* Reset to read array mode */
- *addr = 0xFFFF;
- asm("sync");
- return (flag);
-}
-
-/*-----------------------------------------------------------------------
- * Write a word to Flash, returns:
- * 0 - OK
- * 1 - write timeout
- * 2 - Flash not erased
- */
-static int write_word (flash_info_t *info, ulong dest, ulong data)
-{
- vu_long *addr = (vu_long *)dest;
- ulong start, csr, ready;
- int flag=0;
-
- switch (info->portwidth) {
- case FLASH_CFI_32BIT:
- /* Check if Flash is (sufficiently) erased */
- if ((*addr & data) != data) {
- return (2);
- }
- /* Disable interrupts which might cause a timeout here */
- flag = disable_interrupts();
-
- if (big_endian == 1) {
- ready = 0x0080;
- }
- else {
- ready = 0x8000;
- }
- if ((info->portwidth / info->chipwidth)==2) {
- ready += (ready <<16);
- }
- else {
- ready = ready << 16;
- }
- /* Write Command */
- *addr = 0x10101010;
- asm("sync");
- /* Write Data */
- *addr = data;
- /* re-enable interrupts if necessary */
- if (flag)
- enable_interrupts();
- /* data polling for D7 */
- start = get_timer (0);
- flag = 0;
- while (((csr = *addr) & ready) != ready) {
- if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
- flag = 1;
- break;
- }
- }
- if (csr & 0x40404040) {
- printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
- flag = 1;
- }
- /* Clear Status Registers Command */
- *addr = 0x50505050;
- asm("sync");
- /* Reset to read array mode */
- *addr = 0xFFFFFFFF;
- asm("sync");
- break;
- case FLASH_CFI_16BIT:
- flag = write_short (info, dest, (unsigned short) (data>>16));
- if (flag == 0)
- flag = write_short (info, dest+2, (unsigned short) (data));
- break;
- }
- return (flag);
-}
-
-/*-----------------------------------------------------------------------
- * Clear Block Lock Bit, returns:
- * 0 - OK
- * 1 - Timeout
- */
-
-static int clear_block_lock_bit(flash_info_t * info, vu_long * addr)
-{
- ulong start, now, ready;
-
- /* Reset Array */
- *addr = 0xffffffff;
- asm("sync");
- /* Clear Status Register */
- *addr = 0x50505050;
- asm("sync");
-
- *addr = 0x60606060;
- asm("sync");
- *addr = 0xd0d0d0d0;
- asm("sync");
-
-
- if (big_endian == 1) {
- ready = 0x0080;
- }
- else {
- ready = 0x8000;
- }
- if ((info->portwidth / info->chipwidth)==2) {
- ready += (ready <<16);
- }
- else {
- ready = ready << 16;
- }
-#ifdef DEBUG
- printf ("%s: Ready flag is 0x%8lx\n", __FUNCTION__, ready);
-#endif
- *addr = 0x70707070; /* read status */
- start = get_timer (0);
- while((*addr & ready) != ready){
- if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
- printf ("Timeout on clearing Block Lock Bit\n");
- *addr = 0xFFFFFFFF; /* reset bank */
- asm("sync");
- return 1;
- }
- }
- return 0;
-}
-
-#endif /* !CONFIG_SYS_NO_FLASH */
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/* LAW(Local Access Window) configuration:
- * 0000_0000-0800_0000: DDR(128M) -or- larger
- * f000_0000-f3ff_ffff: PCI(256M)
- * f400_0000-f7ff_ffff: RapidIO(128M)
- * f800_0000-ffff_ffff: localbus(128M)
- * f800_0000-fbff_ffff: LBC SDRAM(64M)
- * fc00_0000-fdef_ffff: LBC BCSR,RTC,etc(31M)
- * fdf0_0000-fdff_ffff: CCSRBAR(1M)
- * fe00_0000-ffff_ffff: Flash(32M)
- * Note: CCSRBAR and L2-as-SRAM don't need configure Local Access
- * Window.
- * Note: If flash is 8M at default position(last 8M),no LAW needed.
- */
-
-struct law_entry law_table[] = {
-#ifndef CONFIG_SPD_EEPROM
- SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
-#endif
- SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
-#ifndef CONFIG_RAM_AS_FLASH
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
-#endif
-};
-
-int num_law_entries = ARRAY_SIZE(law_table);
+++ /dev/null
-/*
- * (C) Copyright 2002,2003, Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_ddr_sdram.h>
-#include <spd_sdram.h>
-
-long int fixed_sdram (void);
-
-int board_pre_init (void)
-{
-#if defined(CONFIG_PCI)
- volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
-
- pci->peer &= 0xffffffdf; /* disable master abort */
-#endif
- return 0;
-}
-
-int checkboard (void)
-{
- sys_info_t sysinfo;
-
- get_sys_info (&sysinfo);
-
- printf ("Board: Freescale MPC8540EVAL Board\n");
- printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor[0] / 1000000);
- printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
- printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
- if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
- || (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
- printf ("\tLBC: %lu MHz\n",
- sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f));
- } else {
- printf("\tLBC: unknown\n");
- }
- printf("L1 D-cache 32KB, L1 I-cache 32KB enabled.\n");
- return (0);
-}
-
-phys_size_t initdram (int board_type)
-{
- long dram_size = 0;
-
-#if !defined(CONFIG_RAM_AS_FLASH)
- volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
- sys_info_t sysinfo;
- uint temp_lbcdll = 0;
-#endif
-#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
- volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#endif
-
-#if defined(CONFIG_DDR_DLL)
- uint temp_ddrdll = 0;
-
- /* Work around to stabilize DDR DLL */
- temp_ddrdll = gur->ddrdllcr;
- gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
- asm("sync;isync;msync");
-#endif
-
-#if defined(CONFIG_SPD_EEPROM)
- dram_size = fsl_ddr_sdram();
- dram_size = setup_ddr_tlbs(dram_size / 0x100000);
- dram_size *= 0x100000;
-#else
- dram_size = fixed_sdram ();
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT)
- return dram_size;
-#endif
-
-#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
- get_sys_info(&sysinfo);
- /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */
- if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) {
- lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
- } else {
- lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
- udelay(200);
- temp_lbcdll = gur->lbcdllcr;
- gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
- asm("sync;isync;msync");
- }
- set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
- set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
- lbc->lbcr = CONFIG_SYS_LBC_LBCR;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
- asm("sync");
- * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
- asm("sync");
- * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
- asm("sync");
- * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
- asm("sync");
- * (ulong *)0 = 0x000000ff;
- lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
- asm("sync");
- lbc->lsrt = CONFIG_SYS_LBC_LSRT;
- asm("sync");
- lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
- asm("sync");
-#endif
-
-#if defined(CONFIG_DDR_ECC)
- {
- /* Initialize all of memory for ECC, then
- * enable errors */
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-
- dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
-
- /* Enable errors for ECC */
- ddr->err_disable = 0x00000000;
- asm("sync;isync;msync");
- }
-#endif
-
- return dram_size;
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
- uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
- uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
- uint *p;
-
- printf("SDRAM test phase 1:\n");
- for (p = pstart; p < pend; p++)
- *p = 0xaaaaaaaa;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0xaaaaaaaa) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test phase 2:\n");
- for (p = pstart; p < pend; p++)
- *p = 0x55555555;
-
- for (p = pstart; p < pend; p++) {
- if (*p != 0x55555555) {
- printf ("SDRAM test fails at: %08x\n", (uint) p);
- return 1;
- }
- }
-
- printf("SDRAM test passed.\n");
- return 0;
-}
-#endif
-
-#if !defined(CONFIG_SPD_EEPROM)
-/*************************************************************************
- * fixed sdram init -- doesn't use serial presence detect.
- ************************************************************************/
-long int fixed_sdram (void)
-{
-#ifndef CONFIG_SYS_RAMBOOT
- volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-
- ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
- ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
- ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
- ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
- ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
- ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
-#if defined (CONFIG_DDR_ECC)
- ddr->err_disable = 0x0000000D;
- ddr->err_sbe = 0x00ff0000;
-#endif
- asm("sync;isync;msync");
- udelay(500);
-#if defined (CONFIG_DDR_ECC)
- /* Enable ECC checking */
- ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
-#else
- ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
-#endif
- asm("sync; isync; msync");
- udelay(500);
-#endif
- return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
-}
-#endif /* !defined(CONFIG_SPD_EEPROM) */
-
-int board_eth_init(bd_t *bis)
-{
- /*
- * This board either has PCI NICs or uses the CPU's TSECs
- * pci_eth_init() will return 0 if no NICs found, so in that case
- * returning -1 will force cpu_eth_init() to be called.
- */
- int num = pci_eth_init(bis);
- return (num <= 0 ? -1 : num);
-}
+++ /dev/null
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1M, 1),
-
- #if defined(CONFIG_SYS_FLASH_PORT_WIDTH_16)
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_4M, 1),
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x400000, CONFIG_SYS_FLASH_BASE + 0x400000,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_4M, 1),
- #else
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_16M, 1),
- #endif
-
- #if !defined(CONFIG_SPD_EEPROM)
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 4, BOOKE_PAGESZ_64M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 5, BOOKE_PAGESZ_64M, 1),
- #endif
-
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
- #if defined(CONFIG_RAM_AS_FLASH)
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- #else
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- #endif
- 0, 6, BOOKE_PAGESZ_64M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 7, BOOKE_PAGESZ_16K, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 8, BOOKE_PAGESZ_256M, 1),
-
- SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 9, BOOKE_PAGESZ_16K, 1),
-};
-
-int num_tlb_entries = ARRAY_SIZE(tlb_table);
SIMPC8313_LP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_LP
SIMPC8313_SP powerpc mpc83xx simpc8313 sheldon - SIMPC8313:NAND_SP
TQM834x powerpc mpc83xx tqm834x tqc
-MPC8540EVAL powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M
-MPC8540EVAL_33 powerpc mpc85xx mpc8540eval - - MPC8540EVAL
-MPC8540EVAL_33_slave powerpc mpc85xx mpc8540eval - - MPC8540EVAL:PCI_SLAVE
-MPC8540EVAL_66 powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M
-MPC8540EVAL_66_slave powerpc mpc85xx mpc8540eval - - MPC8540EVAL:SYSCLK_66M,PCI_SLAVE
PM854 powerpc mpc85xx pm854
PM856 powerpc mpc85xx pm856
sbc8540 powerpc mpc85xx sbc8560 - - SBC8540
+++ /dev/null
-/*
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Modified by Lunsheng Wang, lunsheng@sohu.com
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/* mpc8540eval board configuration file */
-/* please refer to doc/README.mpc85xxads for more info */
-/* make sure you change the MAC address and other network params first,
- * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-/* High Level Configuration Options */
-#define CONFIG_BOOKE 1 /* BOOKE */
-#define CONFIG_E500 1 /* BOOKE e500 family */
-#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
-#define CONFIG_MPC8540 1 /* MPC8540 specific */
-#define CONFIG_MPC8540EVAL 1 /* MPC8540EVAL board specific */
-
-#define CONFIG_SYS_TEXT_BASE 0xfff80000
-
-#undef CONFIG_PCI /* pci ethernet support */
-#define CONFIG_TSEC_ENET /* tsec ethernet support */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-
-/* Using Localbus SDRAM to emulate flash before we can program the flash,
- * normally you only need a flash-boot image(u-boot.bin),if unsure undef this.
- * Not availabe for EVAL board
- */
-#undef CONFIG_RAM_AS_FLASH
-
-/* sysclk for MPC8540EVAL */
-#if defined(CONFIG_SYSCLK_66M)
- /*
- * the oscillator on board is 66Mhz
- * can also get 66M clock from external PCI
- */
- #define CONFIG_SYS_CLK_FREQ 66000000
-#else
- #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
-#endif
-
-/* below can be toggled for performance analysis. otherwise use default */
-#define CONFIG_L2_CACHE /* toggle L2 cache */
-#undef CONFIG_BTB /* toggle branch predition */
-
-#define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */
-
-#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
-#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x00400000
-
-#if defined(CONFIG_PCI) && defined(CONFIG_TSEC_ENET)
-#error "You can only use either PCI Ethernet Card or TSEC Ethernet, not both."
-#endif
-
-/*
- * Base addresses -- Note these are effective addresses where the
- * actual resources get mapped (not physical addresses)
- */
-#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
-#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
-#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
-#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
-
-#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is now 256MB */
-
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */
-#else
-#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
-#endif
-#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 0MB */
-
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 16M */
-#define CONFIG_SYS_BR0_PRELIM 0xf8001801 /* port size 32bit */
-#else /* Boot from real Flash */
-#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
-#define CONFIG_SYS_BR0_PRELIM 0xff801001 /* port size 16bit */
-#endif
-
-#define CONFIG_SYS_OR0_PRELIM 0xff806f67 /* 8MB Flash */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
-#undef CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms)*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms)*/
-#define CONFIG_SYS_FLASH_CFI 1
-
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
-
-#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
-#define CONFIG_SYS_RAMBOOT
-#else
-#undef CONFIG_SYS_RAMBOOT
-#endif
-
-/* DDR Setup */
-#define CONFIG_FSL_DDR1
-#undef CONFIG_FSL_DDR_INTERACTIVE
-#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
-#define CONFIG_DDR_SPD
-#define CONFIG_DDR_DLL /* possible DLL fix needed */
-
-#undef CONFIG_DDR_ECC /* only for ECC DDR module */
-#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
-#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
-
-#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
-#define CONFIG_VERY_BIG_RAM
-
-#define CONFIG_NUM_DDR_CONTROLLERS 1
-#define CONFIG_DIMM_SLOTS_PER_CTLR 1
-#define CONFIG_CHIP_SELECTS_PER_CTRL 2
-
-/* I2C addresses of SPD EEPROMs */
-#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
-
-#undef CONFIG_CLOCKS_IN_MHZ
-
-/* local bus definitions */
-#define CONFIG_SYS_BR2_PRELIM 0xf0001861 /* 64MB localbus SDRAM */
-#define CONFIG_SYS_OR2_PRELIM 0xfc006901
-#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq divider*/
-#define CONFIG_SYS_LBC_LBCR 0x00000000
-#define CONFIG_SYS_LBC_LSRT 0x20000000
-#define CONFIG_SYS_LBC_MRTPR 0x20000000
-#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
-#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
-#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
-#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
-
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CONFIG_SYS_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
-#else
-#define CONFIG_SYS_BR4_PRELIM 0xf8000801 /* 32KB, 8-bit wide for ADS config reg */
-#endif
-#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
-#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
-
-#define CONFIG_SYS_INIT_RAM_LOCK 1
-#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
-#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
-
-/* Serial Port */
-#define CONFIG_CONS_INDEX 1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
-#define CONFIG_BAUDRATE 115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE \
- {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
-
-#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
-
-/* Use the HUSH parser */
-#define CONFIG_SYS_HUSH_PARSER
-#ifdef CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
-#endif
-
-/*
- * I2C
- */
-#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
-#define CONFIG_HARD_I2C /* I2C with hardware support*/
-#undef CONFIG_SOFT_I2C /* I2C bit-banged */
-#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
-#define CONFIG_SYS_I2C_OFFSET 0x3000
-
-/* General PCI */
-#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
-#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
-#define CONFIG_SYS_PCI_MEM_SIZE 0x20000000
-#define CONFIG_SYS_PCI_IO_BASE 0xe2000000
-
-#if defined(CONFIG_PCI)
-#define CONFIG_NET_MULTI
-#undef CONFIG_EEPRO100
-#define CONFIG_TULIP
-#define CONFIG_PCI_PNP /* do pci plug-and-play */
-#if !defined(CONFIG_PCI_PNP)
-#define PCI_ENET0_IOADDR 0xe0000000
-#define PCI_ENET0_MEMADDR 0xe0000000
-#define PCI_IDSEL_NUMBER 0x0c /*slot0->3(IDSEL)=12->15*/
-#endif
-#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0008
-#elif defined(CONFIG_TSEC_ENET)
-#define CONFIG_NET_MULTI 1
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_TSEC1 1
-#define CONFIG_HAS_ETH0
-#define CONFIG_TSEC1_NAME "TSEC0"
-#define CONFIG_TSEC2 1
-#define CONFIG_HAS_ETH1
-#define CONFIG_TSEC2_NAME "TSEC1"
-#define CONFIG_MPC85XX_FEC 1
-#define CONFIG_HAS_ETH2
-#define CONFIG_MPC85XX_FEC_NAME "FEC"
-#define TSEC1_PHY_ADDR 7
-#define TSEC2_PHY_ADDR 4
-#define FEC_PHY_ADDR 2
-#define TSEC1_PHYIDX 0
-#define TSEC2_PHYIDX 0
-#define FEC_PHYIDX 0
-#define TSEC1_FLAGS TSEC_GIGABIT
-#define TSEC2_FLAGS TSEC_GIGABIT
-#define FEC_FLAGS 0
-
-/* Options are: TSEC[0-1], FEC */
-#define CONFIG_ETHPRIME "TSEC0"
-
-#define CONFIG_PHY_M88E1011 1 /* GigaBit Ether PHY */
-#define INTEL_LXT971_PHY 1
-#endif
-
-/* Environment */
-#ifndef CONFIG_SYS_RAMBOOT
-#if defined(CONFIG_RAM_AS_FLASH)
-#define CONFIG_ENV_IS_NOWHERE
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x100000)
-#define CONFIG_ENV_SIZE 0x2000
-#else
-#define CONFIG_ENV_IS_IN_FLASH 1
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
-#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
-#endif
-#define CONFIG_ENV_SIZE 0x2000
-#else
-/* #define CONFIG_SYS_NO_FLASH 1 */ /* Flash is not usable now */
-#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
-#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
-#define CONFIG_ENV_SIZE 0x2000
-#endif
-
-#define CONFIG_BOOTARGS "root=/dev/ram rw console=ttyS0,115200"
-#define CONFIG_BOOTCOMMAND "bootm 0xff800000 0xffa00000"
-#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
-
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
- #define CONFIG_CMD_PCI
-#endif
-
-#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_RAM_AS_FLASH)
- #undef CONFIG_CMD_SAVEENV
- #undef CONFIG_CMD_LOADS
-#endif
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
-#define CONFIG_SYS_PROMPT "MPC8540EVAL=> "/* Monitor Command Prompt */
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
-#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
-#endif
-
-/*****************************/
-/* Environment Configuration */
-/*****************************/
-/* The mac addresses for all ethernet interface */
-/* NOTE: change below for your network setting!!! */
-#if defined(CONFIG_TSEC_ENET)
-#define CONFIG_ETHADDR 00:01:af:07:9b:8a
-#define CONFIG_ETH1ADDR 00:01:af:07:9b:8b
-#define CONFIG_ETH2ADDR 00:01:af:07:9b:8c
-#endif
-
-#define CONFIG_ROOTPATH /nfsroot
-#define CONFIG_BOOTFILE your.uImage
-
-#define CONFIG_SERVERIP 192.168.101.1
-#define CONFIG_IPADDR 192.168.101.11
-#define CONFIG_GATEWAYIP 192.168.101.0
-#define CONFIG_NETMASK 255.255.255.0
-
-#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
-
-#define CONFIG_HOSTNAME MPC8540EVAL
-
-#endif /* __CONFIG_H */
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