ARM: dts: Group omap3 CM_FCLKEN1_CORE clocks

The clksel related registers on omap3 cause unique_unit_address and
node_name_chars_strict warnings with the W=1 or W=2 make flags enabled.

With the clock drivers updated, we can now avoid most of these warnings
by grouping the TI component clocks using the TI clksel binding, and
with the use of clock-output-names property to avoid non-standard node
names for the clocks.

Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/am35xx-clocks.dtsi b/arch/arm/boot/dts/am35xx-clocks.dtsi
index 220d0a5..93a12dd 100644 (file)
--- a/arch/arm/boot/dts/am35xx-clocks.dtsi
+++ b/arch/arm/boot/dts/am35xx-clocks.dtsi
@@ -90,12 +90,19 @@
                ti,bit-shift = <23>;
        };
 
-       uart4_fck_am35xx: uart4_fck_am35xx@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_48m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <23>;
+       clock@a00 {
+               compatible = "ti,clksel";
+               reg = <0xa00>;
+               #clock-cells = <2>;
+               #address-cells = <0>;
+
+               uart4_fck_am35xx: clock-uart4-fck-am35xx {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "uart4_fck_am35xx";
+                       clocks = <&core_48m_fck>;
+                       ti,bit-shift = <23>;
+               };
        };
 };
 

diff --git a/arch/arm/boot/dts/omap3430es1-clocks.dtsi b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
index 2ec3628..6509ae0 100644 (file)
--- a/arch/arm/boot/dts/omap3430es1-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3430es1-clocks.dtsi
@@ -46,28 +46,35 @@
                ti,bit-shift = <2>;
        };
 
-       d2d_26m_fck: d2d_26m_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&sys_ck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <3>;
-       };
-
-       fshostusb_fck: fshostusb_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_48m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <5>;
-       };
-
-       ssi_ssr_gate_fck_3430es1: ssi_ssr_gate_fck_3430es1@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,composite-no-wait-gate-clock";
-               clocks = <&corex2_fck>;
-               ti,bit-shift = <0>;
-               reg = <0x0a00>;
+       clock@a00 {
+               compatible = "ti,clksel";
+               reg = <0xa00>;
+               #clock-cells = <2>;
+               #address-cells = <0>;
+
+               d2d_26m_fck: clock-d2d-26m-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "d2d_26m_fck";
+                       clocks = <&sys_ck>;
+                       ti,bit-shift = <3>;
+               };
+
+               fshostusb_fck: clock-fshostusb-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "fshostusb_fck";
+                       clocks = <&core_48m_fck>;
+                       ti,bit-shift = <5>;
+               };
+
+               ssi_ssr_gate_fck_3430es1: clock-ssi-ssr-gate-fck-3430es1 {
+                       #clock-cells = <0>;
+                       compatible = "ti,composite-no-wait-gate-clock";
+                       clock-output-names = "ssi_ssr_gate_fck_3430es1";
+                       clocks = <&corex2_fck>;
+                       ti,bit-shift = <0>;
+               };
        };
 
        ssi_ssr_div_fck_3430es1: ssi_ssr_div_fck_3430es1@a40 {

diff --git a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
index 21079cd..37556b4 100644 (file)
--- a/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap34xx-omap36xx-clocks.dtsi
@@ -187,14 +187,28 @@
                ti,bit-shift = <0>;
        };
 
-       modem_fck: modem_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,omap3-interface-clock";
-               clocks = <&sys_ck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <31>;
-       };
+       clock@a00 {
+               compatible = "ti,clksel";
+               reg = <0xa00>;
+               #clock-cells = <2>;
+               #address-cells = <0>;
+
+               modem_fck: clock-modem-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,omap3-interface-clock";
+                       clock-output-names = "modem_fck";
+                       clocks = <&sys_ck>;
+                       ti,bit-shift = <31>;
+               };
 
+               mspro_fck: clock-mspro-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "mspro_fck";
+                       clocks = <&core_96m_fck>;
+                       ti,bit-shift = <23>;
+               };
+       };
        sad2d_ick: sad2d_ick@a10 {
                #clock-cells = <0>;
                compatible = "ti,omap3-interface-clock";
@@ -211,13 +225,6 @@
                ti,bit-shift = <3>;
        };
 
-       mspro_fck: mspro_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_96m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <23>;
-       };
 };
 
 &cm_clockdomains {

diff --git a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
index 9974d52..d698b05 100644 (file)
--- a/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-am35xx-omap3430es2plus-clocks.dtsi
@@ -149,12 +149,19 @@
                ti,bit-shift = <30>;
        };
 
-       mmchs3_fck: mmchs3_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_96m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <30>;
+       clock@a00 {
+               compatible = "ti,clksel";
+               reg = <0xa00>;
+               #clock-cells = <2>;
+               #address-cells = <0>;
+
+               mmchs3_fck: clock-mmchs3-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "mmchs3_fck";
+                       clocks = <&core_96m_fck>;
+                       ti,bit-shift = <30>;
+               };
        };
 
        dss1_alwon_fck: dss1_alwon_fck_3430es2@e00 {

diff --git a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
index 945537a..2472363 100644 (file)
--- a/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
+++ b/arch/arm/boot/dts/omap36xx-omap3430es2plus-clocks.dtsi
@@ -5,12 +5,19 @@
  * Copyright (C) 2013 Texas Instruments, Inc.
  */
 &cm_clocks {
-       ssi_ssr_gate_fck_3430es2: ssi_ssr_gate_fck_3430es2@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,composite-no-wait-gate-clock";
-               clocks = <&corex2_fck>;
-               ti,bit-shift = <0>;
-               reg = <0x0a00>;
+       clock@a00 {
+               compatible = "ti,clksel";
+               reg = <0xa00>;
+               #clock-cells = <2>;
+               #address-cells = <0>;
+
+               ssi_ssr_gate_fck_3430es2: clock-ssi-ssr-gate-fck-3430es2 {
+                       #clock-cells = <0>;
+                       compatible = "ti,composite-no-wait-gate-clock";
+                       clock-output-names = "ssi_ssr_gate_fck_3430es2";
+                       clocks = <&corex2_fck>;
+                       ti,bit-shift = <0>;
+               };
        };
 
        ssi_ssr_div_fck_3430es2: ssi_ssr_div_fck_3430es2@a40 {

diff --git a/arch/arm/boot/dts/omap3xxx-clocks.dtsi b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
index 7518fd5..20b8559 100644 (file)
--- a/arch/arm/boot/dts/omap3xxx-clocks.dtsi
+++ b/arch/arm/boot/dts/omap3xxx-clocks.dtsi
@@ -603,12 +603,140 @@
                ti,index-starts-at-one;
        };
 
-       gpt10_gate_fck: gpt10_gate_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,composite-gate-clock";
-               clocks = <&sys_ck>;
-               ti,bit-shift = <11>;
-               reg = <0x0a00>;
+       /* CM_FCLKEN1_CORE */
+       clock@a00 {
+               compatible = "ti,clksel";
+               reg = <0xa00>;
+               #clock-cells = <2>;
+               #address-cells = <0>;
+
+               gpt10_gate_fck: clock-gpt10-gate-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,composite-gate-clock";
+                       clock-output-names = "gpt10_gate_fck";
+                       clocks = <&sys_ck>;
+                       ti,bit-shift = <11>;
+               };
+
+               gpt11_gate_fck: clock-gpt11-gate-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,composite-gate-clock";
+                       clock-output-names = "gpt11_gate_fck";
+                       clocks = <&sys_ck>;
+                       ti,bit-shift = <12>;
+               };
+
+               mmchs2_fck: clock-mmchs2-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "mmchs2_fck";
+                       clocks = <&core_96m_fck>;
+                       ti,bit-shift = <25>;
+               };
+
+               mmchs1_fck: clock-mmchs1-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "mmchs1_fck";
+                       clocks = <&core_96m_fck>;
+                       ti,bit-shift = <24>;
+               };
+
+               i2c3_fck: clock-i2c3-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "i2c3_fck";
+                       clocks = <&core_96m_fck>;
+                       ti,bit-shift = <17>;
+               };
+
+               i2c2_fck: clock-i2c2-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "i2c2_fck";
+                       clocks = <&core_96m_fck>;
+                       ti,bit-shift = <16>;
+               };
+
+               i2c1_fck: clock-i2c1-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "i2c1_fck";
+                       clocks = <&core_96m_fck>;
+                       ti,bit-shift = <15>;
+               };
+
+               mcbsp5_gate_fck: clock-mcbsp5-gate-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,composite-gate-clock";
+                       clock-output-names = "mcbsp5_gate_fck";
+                       clocks = <&mcbsp_clks>;
+                       ti,bit-shift = <10>;
+               };
+
+               mcbsp1_gate_fck: clock-mcbsp1-gate-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,composite-gate-clock";
+                       clock-output-names = "mcbsp1_gate_fck";
+                       clocks = <&mcbsp_clks>;
+                       ti,bit-shift = <9>;
+               };
+
+               mcspi4_fck: clock-mcspi4-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "mcspi4_fck";
+                       clocks = <&core_48m_fck>;
+                       ti,bit-shift = <21>;
+               };
+
+               mcspi3_fck: clock-mcspi3-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "mcspi3_fck";
+                       clocks = <&core_48m_fck>;
+                       ti,bit-shift = <20>;
+               };
+
+               mcspi2_fck: clock-mcspi2-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "mcspi2_fck";
+                       clocks = <&core_48m_fck>;
+                       ti,bit-shift = <19>;
+               };
+
+               mcspi1_fck: clock-mcspi1-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "mcspi1_fck";
+                       clocks = <&core_48m_fck>;
+                       ti,bit-shift = <18>;
+               };
+
+               uart2_fck: clock-uart2-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "uart2_fck";
+                       clocks = <&core_48m_fck>;
+                       ti,bit-shift = <14>;
+               };
+
+               uart1_fck: clock-uart1-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "uart1_fck";
+                       clocks = <&core_48m_fck>;
+                       ti,bit-shift = <13>;
+               };
+
+               hdq_fck: clock-hdq-fck {
+                       #clock-cells = <0>;
+                       compatible = "ti,wait-gate-clock";
+                       clock-output-names = "hdq_fck";
+                       clocks = <&core_12m_fck>;
+                       ti,bit-shift = <22>;
+               };
        };
 
        gpt10_mux_fck: gpt10_mux_fck@a40 {
@@ -625,14 +753,6 @@
                clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
        };
 
-       gpt11_gate_fck: gpt11_gate_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,composite-gate-clock";
-               clocks = <&sys_ck>;
-               ti,bit-shift = <12>;
-               reg = <0x0a00>;
-       };
-
        gpt11_mux_fck: gpt11_mux_fck@a40 {
                #clock-cells = <0>;
                compatible = "ti,composite-mux-clock";
@@ -655,62 +775,6 @@
                clock-div = <1>;
        };
 
-       mmchs2_fck: mmchs2_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_96m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <25>;
-       };
-
-       mmchs1_fck: mmchs1_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_96m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <24>;
-       };
-
-       i2c3_fck: i2c3_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_96m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <17>;
-       };
-
-       i2c2_fck: i2c2_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_96m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <16>;
-       };
-
-       i2c1_fck: i2c1_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_96m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <15>;
-       };
-
-       mcbsp5_gate_fck: mcbsp5_gate_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,composite-gate-clock";
-               clocks = <&mcbsp_clks>;
-               ti,bit-shift = <10>;
-               reg = <0x0a00>;
-       };
-
-       mcbsp1_gate_fck: mcbsp1_gate_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,composite-gate-clock";
-               clocks = <&mcbsp_clks>;
-               ti,bit-shift = <9>;
-               reg = <0x0a00>;
-       };
-
        core_48m_fck: core_48m_fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
@@ -719,54 +783,6 @@
                clock-div = <1>;
        };
 
-       mcspi4_fck: mcspi4_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_48m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <21>;
-       };
-
-       mcspi3_fck: mcspi3_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_48m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <20>;
-       };
-
-       mcspi2_fck: mcspi2_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_48m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <19>;
-       };
-
-       mcspi1_fck: mcspi1_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_48m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <18>;
-       };
-
-       uart2_fck: uart2_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_48m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <14>;
-       };
-
-       uart1_fck: uart1_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_48m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <13>;
-       };
-
        core_12m_fck: core_12m_fck {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";
@@ -775,14 +791,6 @@
                clock-div = <1>;
        };
 
-       hdq_fck: hdq_fck@a00 {
-               #clock-cells = <0>;
-               compatible = "ti,wait-gate-clock";
-               clocks = <&core_12m_fck>;
-               reg = <0x0a00>;
-               ti,bit-shift = <22>;
-       };
-
        core_l3_ick: core_l3_ick {
                #clock-cells = <0>;
                compatible = "fixed-factor-clock";