+2017-01-23 Sebastian Rasmussen <sebras@gmail.com>
+
+ PR gas/21072
+ * asintl.h: Fix spelling mistakes and typos.
+ * atof-generic.c: Likewise.
+ * bit_fix.h: Likewise.
+ * config/atof-ieee.c: Likewise.
+ * config/bfin-defs.h: Likewise.
+ * config/bfin-parse.y: Likewise.
+ * config/obj-coff-seh.h: Likewise.
+ * config/obj-coff.c: Likewise.
+ * config/obj-evax.c: Likewise.
+ * config/obj-macho.c: Likewise.
+ * config/rx-parse.y: Likewise.
+ * config/tc-aarch64.c: Likewise.
+ * config/tc-alpha.c: Likewise.
+ * config/tc-arc.c: Likewise.
+ * config/tc-arm.c: Likewise.
+ * config/tc-avr.c: Likewise.
+ * config/tc-bfin.c: Likewise.
+ * config/tc-cr16.c: Likewise.
+ * config/tc-cris.c: Likewise.
+ * config/tc-crx.c: Likewise.
+ * config/tc-d10v.c: Likewise.
+ * config/tc-d30v.c: Likewise.
+ * config/tc-dlx.c: Likewise.
+ * config/tc-epiphany.c: Likewise.
+ * config/tc-frv.c: Likewise.
+ * config/tc-hppa.c: Likewise.
+ * config/tc-i370.c: Likewise.
+ * config/tc-i386-intel.c: Likewise.
+ * config/tc-i386.c: Likewise.
+ * config/tc-i960.c: Likewise.
+ * config/tc-ia64.c: Likewise.
+ * config/tc-m32r.c: Likewise.
+ * config/tc-m68hc11.c: Likewise.
+ * config/tc-m68k.c: Likewise.
+ * config/tc-mcore.c: Likewise.
+ * config/tc-mep.c: Likewise.
+ * config/tc-mep.h: Likewise.
+ * config/tc-metag.c: Likewise.
+ * config/tc-microblaze.c: Likewise.
+ * config/tc-mips.c: Likewise.
+ * config/tc-mmix.c: Likewise.
+ * config/tc-mn10200.c: Likewise.
+ * config/tc-mn10300.c: Likewise.
+ * config/tc-msp430.c: Likewise.
+ * config/tc-msp430.h: Likewise.
+ * config/tc-nds32.c: Likewise.
+ * config/tc-nds32.h: Likewise.
+ * config/tc-nios2.c: Likewise.
+ * config/tc-nios2.h: Likewise.
+ * config/tc-ns32k.c: Likewise.
+ * config/tc-pdp11.c: Likewise.
+ * config/tc-ppc.c: Likewise.
+ * config/tc-pru.c: Likewise.
+ * config/tc-rx.c: Likewise.
+ * config/tc-s390.c: Likewise.
+ * config/tc-score.c: Likewise.
+ * config/tc-score7.c: Likewise.
+ * config/tc-sh.c: Likewise.
+ * config/tc-sh64.c: Likewise.
+ * config/tc-sparc.c: Likewise.
+ * config/tc-tic4x.c: Likewise.
+ * config/tc-tic54x.c: Likewise.
+ * config/tc-v850.c: Likewise.
+ * config/tc-vax.c: Likewise.
+ * config/tc-visium.c: Likewise.
+ * config/tc-xgate.c: Likewise.
+ * config/tc-xtensa.c: Likewise.
+ * config/tc-z80.c: Likewise.
+ * config/tc-z8k.c: Likewise.
+ * config/te-vms.c: Likewise.
+ * config/xtensa-relax.c: Likewise.
+ * doc/as.texinfo: Likewise.
+ * doc/c-arm.texi: Likewise.
+ * doc/c-hppa.texi: Likewise.
+ * doc/c-i370.texi: Likewise.
+ * doc/c-i386.texi: Likewise.
+ * doc/c-m32r.texi: Likewise.
+ * doc/c-m68k.texi: Likewise.
+ * doc/c-mmix.texi: Likewise.
+ * doc/c-msp430.texi: Likewise.
+ * doc/c-nds32.texi: Likewise.
+ * doc/c-ns32k.texi: Likewise.
+ * doc/c-riscv.texi: Likewise.
+ * doc/c-rx.texi: Likewise.
+ * doc/c-s390.texi: Likewise.
+ * doc/c-tic6x.texi: Likewise.
+ * doc/c-tilegx.texi: Likewise.
+ * doc/c-tilepro.texi: Likewise.
+ * doc/c-v850.texi: Likewise.
+ * doc/c-xgate.texi: Likewise.
+ * doc/c-xtensa.texi: Likewise.
+ * dwarf2dbg.c: Likewise.
+ * ecoff.c: Likewise.
+ * itbl-ops.c: Likewise.
+ * listing.c: Likewise.
+ * macro.c: Likewise.
+ * po/gas.pot: Likewise.
+ * read.c: Likewise.
+ * struc-symbol.h: Likewise.
+ * symbols.h: Likewise.
+ * testsuite/gas/arc/relocs-errors.err: Likewise.
+ * write.c: Likewise.
+
2017-01-23 Nick Clifton <nickc@redhat.com>
* po/sv.po: Updated Swedish translation.
/* The Solaris version of locale.h always includes libintl.h. If we have
been configured with --disable-nls then ENABLE_NLS will not be defined
and the dummy definitions of bindtextdomain (et al) below will conflict
- with the defintions in libintl.h. So we define these values to prevent
+ with the definitions in libintl.h. So we define these values to prevent
the bogus inclusion of libintl.h. */
# define _LIBINTL_H
# define _LIBGETTEXT_H
{
/*
- * Compute the mantssa (& exponent) of the power of 10.
+ * Compute the mantissa (& exponent) of the power of 10.
* If successful, then multiply the power of 10 by the digits
* giving return_binary_mantissa and return_binary_exponent.
*/
/* The bit_fix was implemented to support machines that need variables
to be inserted in bitfields other than 1, 2 and 4 bytes.
Furthermore it gives us a possibility to mask in bits in the symbol
- when it's fixed in the objectcode and check the symbols limits.
+ when it's fixed in the object code and check the symbols limits.
The or-mask is used to set the huffman bits in displacements for the
ns32k port.
can come from the .dc.s, .dcb.s, .float or .single pseudo-ops and the
'd' type from the .dc.d, .dbc.d or .double pseudo-ops.
- The 'x' type is not implicitly recongised however, even though it can
+ The 'x' type is not implicitly recognised however, even though it can
be generated by the .dc.x and .dbc.x pseudo-ops because not all targets
can support floating point values that big. ie the target has to
explicitly allow them by putting them into FLT_CHARS. */
#define T_REG_A 0x40
/* All registers above this value don't
- belong to a usuable register group. */
+ belong to a usable register group. */
#define T_NOGROUP 0xa0
/* Flags. */
else if (is_group2 ($3) && is_group1 ($5))
$$ = gen_multi_instr_1 ($1, $5, $3);
else
- return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instrution group");
+ return yyerror ("Wrong 16 bit instructions groups, slot 2 and slot 3 must be 16-bit instruction group");
}
else if (($3->value & 0xf800) == 0xc000)
{
else if (is_group2 ($1) && is_group1 ($5))
$$ = gen_multi_instr_1 ($3, $5, $1);
else
- return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instrution group");
+ return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 3 must be 16-bit instruction group");
}
else if (($5->value & 0xf800) == 0xc000)
{
else if (is_group2 ($1) && is_group1 ($3))
$$ = gen_multi_instr_1 ($5, $3, $1);
else
- return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instrution group");
+ return yyerror ("Wrong 16 bit instructions groups, slot 1 and slot 2 must be 16-bit instruction group");
}
else
error ("\nIllegal Multi Issue Construct, at least any one of the slot must be DSP32 instruction group\n");
The third version has a function entry block of BeginAddress (RVA),
EndAddress (RVA), and UnwindData (RVA). The description of the
- prologue, excepetion-handler, and additional SEH data is stored
+ prologue, exception-handler, and additional SEH data is stored
within the UNWIND_DATA field in the xdata section.
The pseudos:
{
if (def_symbol_in_progress == NULL)
{
- as_warn (_(".size pseudo-op used outside of .def/.endef ignored."));
+ as_warn (_(".size pseudo-op used outside of .def/.endef: ignored."));
demand_empty_rest_of_line ();
return;
}
{
if (def_symbol_in_progress == NULL)
{
- as_warn (_(".scl pseudo-op used outside of .def/.endef ignored."));
+ as_warn (_(".scl pseudo-op used outside of .def/.endef: ignored."));
demand_empty_rest_of_line ();
return;
}
if (def_symbol_in_progress == NULL)
{
- as_warn (_(".tag pseudo-op used outside of .def/.endef ignored."));
+ as_warn (_(".tag pseudo-op used outside of .def/.endef: ignored."));
demand_empty_rest_of_line ();
return;
}
{
if (def_symbol_in_progress == NULL)
{
- as_warn (_(".type pseudo-op used outside of .def/.endef ignored."));
+ as_warn (_(".type pseudo-op used outside of .def/.endef: ignored."));
demand_empty_rest_of_line ();
return;
}
{
if (def_symbol_in_progress == NULL)
{
- as_warn (_(".val pseudo-op used outside of .def/.endef ignored."));
+ as_warn (_(".val pseudo-op used outside of .def/.endef: ignored."));
demand_empty_rest_of_line ();
return;
}
/* The length is computed from the maximum allowable length of 64 less the
4 character ..xx extension that must be preserved (removed before
- krunching and appended back on afterwards). The $<nnn>.. prefix is
+ crunching and appended back on afterwards). The $<nnn>.. prefix is
also removed and prepened back on, but doesn't enter into the length
computation because symbols with that prefix are always resolved
by the assembler and will never appear in the symbol table. At least
}
}
- /* We only need worry about krunching the base symbol. */
+ /* We only need worry about crunching the base symbol. */
base_id = xmemdup0 (&id[prefix_dotdot], suffix_dotdot - prefix_dotdot);
if (strlen (base_id) > MAX_LABEL_LENGTH)
an integer. */
static char decodings[256];
-/* Table used by the crc32 function to calcuate the checksum. */
+/* Table used by the crc32 function to calculate the checksum. */
static unsigned int crc32_table[256] = {0, 0};
/* Given a string in BUF, calculate a 32-bit CRC for it.
{
if (ptr[0] == '_' && ptr[1] == 'h')
{
- /* Now see if the sum encoded in the identifer matches. */
+ /* Now see if the sum encoded in the identifier matches. */
int x, sum;
sum = 0;
for (x = 0; x < 5; x++)
attributes along with the canonical name. */
xlat = bfd_mach_o_section_data_for_mach_sect (stdoutput, segname, sectname);
- /* TODO: more checking of whether overides are acually allowed. */
+ /* TODO: more checking of whether overrides are actually allowed. */
if (xlat != NULL)
{
if ((sectype == BFD_MACH_O_S_ZEROFILL
|| sectype == BFD_MACH_O_S_GB_ZEROFILL)
&& sectype != usectype)
- as_bad (_("cannot overide zerofill section type for `%s,%s'"),
+ as_bad (_("cannot override zerofill section type for `%s,%s'"),
segname, sectname);
else
sectype = usectype;
md_flush_pending_output ();
#endif
- /* Get the User's segment annd section names. */
+ /* Get the User's segment and section names. */
if (! obj_mach_o_get_section_names (segname, sectname, 17, 17))
return;
md_flush_pending_output ();
#endif
- /* Get the User's segment annd section names. */
+ /* Get the User's segment and section names. */
if (! obj_mach_o_get_section_names (segname, sectname, 17, 17))
return;
static int
immediate (expressionS exp, int type, int pos, int bits)
{
- /* We will emit constants ourself here, so negate them. */
+ /* We will emit constants ourselves here, so negate them. */
if (type == RXREL_NEGATIVE && exp.X_op == O_constant)
exp.X_add_number = - exp.X_add_number;
if (type == RXREL_NEGATIVE_BORROW)
static bfd_boolean parse_operands (char *, const aarch64_opcode *);
static bfd_boolean programmer_friendly_fixup (aarch64_instruction *);
-/* Diagnostics inline function utilites.
+/* Diagnostics inline function utilities.
- These are lightweight utlities which should only be called by parse_operands
+ These are lightweight utilities which should only be called by parse_operands
and other parsers. GAS processes each assembly line by parsing it against
instruction template(s), in the case of multiple templates (for the same
mnemonic name), those templates are tried one by one until one succeeds or
the parsing; we don't want to slow down the whole parsing by recording
non-user errors in detail.
- Remember that the objective is to help GAS pick up the most approapriate
+ Remember that the objective is to help GAS pick up the most appropriate
error message in the case of multiple templates, e.g. FMOV which has 8
templates. */
/* Expect index. In the new scheme we cannot have
Vn.[bhsdq] represent a scalar. Therefore any
Vn.[bhsdq] should have an index following it.
- Except in reglists ofcourse. */
+ Except in reglists of course. */
atype.defined |= NTA_HASINDEX;
else
atype.defined |= NTA_HASTYPE;
}
/* Can't use symbol_new here, so have to create a symbol and then at
- a later date assign it a value. Thats what these functions do. */
+ a later date assign it a value. That's what these functions do. */
static void
symbol_locate (symbolS * symbolP,
return inst.reloc.type == BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP;
}
-/* Assign the immediate value to the relavant field in *OPERAND if
+/* Assign the immediate value to the relevant field in *OPERAND if
RELOC->EXP is a constant expression; otherwise, flag that *OPERAND
needs an internal fixup in a later stage.
ADDR_OFF_P determines whether it is the field ADDR.OFFSET.IMM or
/* Get to the page containing GOT TLS entry for a symbol.
The same as GD, we allocate two consecutive GOT slots
for module index and module offset, the only difference
- with GD is the module offset should be intialized to
+ with GD is the module offset should be initialized to
zero without any outstanding runtime relocation. */
{"tlsldm", 0,
BFD_RELOC_AARCH64_TLSLD_ADR_PREL21, /* adr_type */
instruction->reloc.type = BFD_RELOC_UNUSED;
}
-/* Data strutures storing one user error in the assembly code related to
+/* Data structures storing one user error in the assembly code related to
operands. */
struct operand_error_record
return idx;
}
-/* Assign qualifiers in the qualifier seqence (headed by QUALIFIERS) to the
+/* Assign qualifiers in the qualifier sequence (headed by QUALIFIERS) to the
corresponding operands in *INSTR. */
static inline void
When this function is called, the operand error information had
been collected for an assembly line and there will be multiple
- errors in the case of mulitple instruction templates; output the
+ errors in the case of multiple instruction templates; output the
error message that most closely describes the problem. */
static void
}
/* Find the error kind of the highest severity. */
- DEBUG_TRACE ("multiple opcode entres with error kind");
+ DEBUG_TRACE ("multiple opcode entries with error kind");
kind = AARCH64_OPDE_NIL;
for (curr = head; curr != NULL; curr = curr->next)
{
return TRUE;
}
-/* A primitive log caculator. */
+/* A primitive log calculator. */
static inline unsigned int
get_logsz (unsigned int size)
gas_assert (logsz <= 4);
/* In reloc.c, these pseudo relocation types should be defined in similar
- order as above reloc_ldst_lo12 array. Because the array index calcuation
+ order as above reloc_ldst_lo12 array. Because the array index calculation
below relies on this. */
return reloc_ldst_lo12[inst.reloc.type - BFD_RELOC_AARCH64_LDST_LO12][logsz];
}
backtrack_pos = str;
}
- /* Expect comma between operands; the backtrack mechanizm will take
+ /* Expect comma between operands; the backtrack mechanism will take
care of cases of omitted optional operand. */
if (i > 0 && ! skip_past_char (&str, ','))
{
Note - despite the name this initialisation is not done when the frag
is created, but only when its type is assigned. A frag can be created
and used a long time before its type is set, so beware of assuming that
- this initialisationis performed first. */
+ this initialisation is performed first. */
#ifndef OBJ_ELF
void
present. Not implemented.
Also suppress the optimization if the !literals/!lituses are spread
- in different segments. This can happen with "intersting" uses of
+ in different segments. This can happen with "interesting" uses of
inline assembly; examples are present in the Linux kernel semaphores. */
for (fixp = seginfo->fix_root; fixp; fixp = next)
#ifdef OBJ_EVAX
/* Add sym+addend to link pool.
- Return offset from curent procedure value (pv) to entry in link pool.
+ Return offset from current procedure value (pv) to entry in link pool.
Add new fixup only if offset isn't 16bit. */
}
/* Handle floating point allocation pseudo-ops. This is like the
- generic vresion, but it makes sure the current label, if any, is
+ generic version, but it makes sure the current label, if any, is
correctly aligned. */
static void
relocationsym:
- /* A relocation opernad has the following form
+ /* A relocation operand has the following form
@identifier@relocation_type. The identifier is already
in tok! */
if (tok->X_op != O_symbol)
return 0; /* No space left. */
if (cidx > ntok)
- return 0; /* Incorect args. */
+ return 0; /* Incorrect args. */
memcpy (&tok[ntok+1], &tok[ntok], sizeof (*tok));
if (val < min || val > max)
goto match_failed;
- /* Check alignmets. */
+ /* Check alignments. */
if ((operand->flags & ARC_OPERAND_ALIGNED32)
&& (val & 0x03))
goto match_failed;
return entry;
}
-/* Given an opcode name, pre-tockenized set of argumenst and the
+/* Given an opcode name, pre-tokenized set of arguments and the
opcode flags, take it all the way through emission. */
static void
opnamelen = strspn (str, "abcdefghijklmnopqrstuvwxyz_0123468");
opname = xmemdup0 (str, opnamelen);
- /* Signalize we are assmbling the instructions. */
+ /* Signalize we are assembling the instructions. */
assembling_insn = TRUE;
/* Tokenize the flags. */
return base;
}
-/* Given a BFD relocation find the coresponding operand. */
+/* Given a BFD relocation find the corresponding operand. */
static const struct arc_operand *
find_operand_for_reloc (extended_bfd_reloc_code_real_type reloc)
case BFD_RELOC_ARC_32_ME:
/* This is a pc-relative value in a LIMM. Adjust it to the
address of the instruction not to the address of the
- LIMM. Note: it is not anylonger valid this afirmation as
+ LIMM. Note: it is not any longer valid this affirmation as
the linker consider ARC_PC32 a fixup to entire 64 bit
insn. */
fixP->fx_offset += fixP->fx_frag->fr_address;
return;
}
- /* Addjust the value if we have a constant. */
+ /* Adjust the value if we have a constant. */
value += fx_offset;
/* For hosts with longs bigger than 32-bits make sure that the top
case O_plt:
if (opcode->insn_class == JUMP)
as_bad_where (frag_now->fr_file, frag_now->fr_line,
- _("Unable to use @plt relocatio for insn %s"),
+ _("Unable to use @plt relocation for insn %s"),
opcode->name);
needGOTSymbol = TRUE;
reloc = find_reloc ("plt", opcode->name,
[2]: Value.
[3]+ Name.
- For auxilirary registers:
+ For auxiliary registers:
[2..5]: Value.
[6]+ Name
Some Thumb instructions are alignment-sensitive modulo 4 bytes,
but themselves require 2-byte alignment; this applies to some
- PC- relative forms. However, these cases will invovle implicit
+ PC- relative forms. However, these cases will involve implicit
literal pool generation or an explicit .align >=2, both of
which will cause the section to me marked with sufficient
alignment. Thus, we don't handle those cases here. */
}
/* Can't use symbol_new here, so have to create a symbol and then at
- a later date assign it a value. Thats what these functions do. */
+ a later date assign it a value. That's what these functions do. */
static void
symbol_locate (symbolS * symbolP,
OP_APSR_RR, /* ARM register or "APSR_nzcv". */
OP_RRnpc_I0, /* ARM register or literal 0 */
- OP_RR_EXr, /* ARM register or expression with opt. reloc suff. */
+ OP_RR_EXr, /* ARM register or expression with opt. reloc stuff. */
OP_RR_EXi, /* ARM register or expression with imm prefix */
OP_RF_IF, /* FPA register or immediate */
OP_RIWR_RIWC, /* iWMMXt R or C reg */
top = (inst.instruction & 0x00400000) != 0;
constraint (top && inst.reloc.type == BFD_RELOC_ARM_MOVW,
- _(":lower16: not allowed this instruction"));
+ _(":lower16: not allowed in this instruction"));
constraint (!top && inst.reloc.type == BFD_RELOC_ARM_MOVT,
- _(":upper16: not allowed instruction"));
+ _(":upper16: not allowed in this instruction"));
inst.instruction |= inst.operands[0].reg << 12;
if (inst.reloc.type == BFD_RELOC_UNUSED)
{
}
/* Parse an add or subtract instruction. We get here with inst.instruction
- equalling any of THUMB_OPCODE_add, adds, sub, or subs. */
+ equaling any of THUMB_OPCODE_add, adds, sub, or subs. */
static void
do_t_add_sub (void)
top = (inst.instruction & 0x00800000) != 0;
if (inst.reloc.type == BFD_RELOC_ARM_MOVW)
{
- constraint (top, _(":lower16: not allowed this instruction"));
+ constraint (top, _(":lower16: not allowed in this instruction"));
inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVW;
}
else if (inst.reloc.type == BFD_RELOC_ARM_MOVT)
{
- constraint (!top, _(":upper16: not allowed this instruction"));
+ constraint (!top, _(":upper16: not allowed in this instruction"));
inst.reloc.type = BFD_RELOC_ARM_THUMB_MOVT;
}
set_it_insn_type_last () ditto
in_it_block () ditto
it_fsm_post_encode () from md_assemble ()
- force_automatic_it_block_close () from label habdling functions
+ force_automatic_it_block_close () from label handling functions
Rationale:
1) md_assemble () calls it_fsm_pre_encode () before calling tencode (),
Note - despite the name this initialisation is not done when the frag
is created, but only when its type is assigned. A frag can be created
and used a long time before its type is set, so beware of assuming that
- this initialisationis performed first. */
+ this initialisation is performed first. */
#ifndef OBJ_ELF
void
{"softvfp+vfp", FPU_ARCH_VFP_V2},
{"vfp", FPU_ARCH_VFP_V2},
{"vfp9", FPU_ARCH_VFP_V2},
- {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatbility. */
+ {"vfp3", FPU_ARCH_VFP_V3}, /* For backwards compatibility. */
{"vfp10", FPU_ARCH_VFP_V2},
{"vfp10-r0", FPU_ARCH_VFP_V1},
{"vfpxd", FPU_ARCH_VFP_V1xD},
static struct mcu_type_s mcu_types[] =
{
{"avr1", AVR_ISA_AVR1, bfd_mach_avr1},
-/* TODO: insruction set for avr2 architecture should be AVR_ISA_AVR2,
+/* TODO: instruction set for avr2 architecture should be AVR_ISA_AVR2,
but set to AVR_ISA_AVR25 for some following version
of GCC (from 4.3) for backward compatibility. */
{"avr2", AVR_ISA_AVR25, bfd_mach_avr2},
{"avr25", AVR_ISA_AVR25, bfd_mach_avr25},
-/* TODO: insruction set for avr3 architecture should be AVR_ISA_AVR3,
+/* TODO: instruction set for avr3 architecture should be AVR_ISA_AVR3,
but set to AVR_ISA_AVR3_ALL for some following version
of GCC (from 4.3) for backward compatibility. */
{"avr3", AVR_ISA_AVR3_ALL, bfd_mach_avr3},
{"avr31", AVR_ISA_AVR31, bfd_mach_avr31},
{"avr35", AVR_ISA_AVR35, bfd_mach_avr35},
{"avr4", AVR_ISA_AVR4, bfd_mach_avr4},
-/* TODO: insruction set for avr5 architecture should be AVR_ISA_AVR5,
+/* TODO: instruction set for avr5 architecture should be AVR_ISA_AVR5,
but set to AVR_ISA_AVR51 for some following version
of GCC (from 4.3) for backward compatibility. */
{"avr5", AVR_ISA_AVR51, bfd_mach_avr5},
specifications with same mnemonic who's ISA bits matches.
This requires include/opcode/avr.h to have the instructions with
- same mnenomic to be specified in sequence. */
+ same mnemonic to be specified in sequence. */
while ((opcode->isa & avr_mcu->isa) != opcode->isa)
{
}
if (bad)
- as_bad (_("illegal %srelocation size: %d"), pexp_mod_data->error, nbytes);
+ as_bad (_("illegal %s relocation size: %d"), pexp_mod_data->error, nbytes);
}
static bfd_boolean
cfi_add_CFA_def_cfa (32, return_size);
/* Note that AVR consistently uses post-decrement, which means that things
- do not line up the same way as for targers that use pre-decrement. */
+ do not line up the same way as for targets that use pre-decrement. */
cfi_add_CFA_offset (DWARF2_DEFAULT_RETURN_COLUMN, 1-return_size);
}
INSTR_T
Expr_Node_Gen_Reloc (Expr_Node * head, int parent_reloc)
{
- /* Top level reloction expression generator VDSP style.
+ /* Top level relocation expression generator VDSP style.
If the relocation is just by itself, generate one item
else generate this convoluted expression. */
INSTR_T note = NULL_CODE;
INSTR_T note1 = NULL_CODE;
- int pcrel = 1; /* Is the parent reloc pcrelative?
+ int pcrel = 1; /* Is the parent reloc pc-relative?
This calculation here and HOWTO should match. */
if (parent_reloc)
const reg_entry *rreg;
char tmp_rp[16]="\0";
- /* Add '(' and ')' to the reg pair, if its not present. */
+ /* Add '(' and ')' to the reg pair, if it's not present. */
if (reg_name[0] != '(')
{
tmp_rp[0] = '(';
static void
set_operand (char *operand, ins * cr16_ins)
{
- char *operandS; /* Pointer to start of sub-opearand. */
- char *operandE; /* Pointer to end of sub-opearand. */
+ char *operandS; /* Pointer to start of sub-operand. */
+ char *operandE; /* Pointer to end of sub-operand. */
argument *cur_arg = &cr16_ins->arg[cur_arg_num]; /* Current argument. */
return 0;
}
-/* Retrieve the opcode image of a given processort register.
+/* Retrieve the opcode image of a given processor register.
If the register is illegal for the current instruction,
issue an error. */
static int
return 0;
}
-/* Retrieve the opcode image of a given processort register.
+/* Retrieve the opcode image of a given processor register.
If the register is illegal for the current instruction,
issue an error. */
static int
/* When instruction size is 3 and 'shift' is 16, a 16-bit constant is
always filling the upper part of output_opcode[1]. If we mistakenly
write it to output_opcode[0], the constant prefix (that is, 'match')
- will be overriden.
+ will be overridden.
0 1 2 3
+---------+---------+---------+---------+
| 'match' | | X X X X | |
if (bits == 0 && value > 0) return OP_OUT_OF_RANGE;
- /* For hosts witah longs bigger than 32-bits make sure that the top
+ /* For hosts with longs bigger than 32-bits make sure that the top
bits of a 32-bit negative value read in by the parser are set,
so that the correct comparisons are made. */
if (value & 0x80000000)
return retval;
}
-/* Bunch of error checkings.
+/* Bunch of error checking.
The checks are made after a matching instruction was found. */
static void
{
unsigned int count = insn->arg[0].constant, reg_val;
- /* Check if count operand caused to save/retrive the RA twice
+ /* Check if count operand caused to save/retrieve the RA twice
to generate warning message. */
if (insn->nargs > 2)
{
goto next_insn;
/* If 'storb' instruction with 'sp' reg and 16-bit disp of
- * reg-pair, leads to undifined trap, so this should use
+ * reg-pair, leads to undefined trap, so this should use
* 20-bit disp of reg-pair. */
if (IS_INSN_MNEMONIC ("storb") && (instruction->size == 2)
&& (insn->arg[i].r == 15) && (insn->arg[i + 1].type == arg_crp))
else
/* Full match - print the encoding to output file. */
{
- /* Make further checkings (such that couldn't be made earlier).
+ /* Make further checking (such that couldn't be made earlier).
Warn the user if necessary. */
warn_if_needed (insn);
;
*param++ = '\0';
- /* bCC instuctions and adjust the mnemonic by adding extra white spaces. */
+ /* bCC instructions and adjust the mnemonic by adding extra white spaces. */
if (is_bcc_insn (op))
{
strcpy (param1, get_b_cc (op));
/* MAPPING - SHIFT INSN, if imm4/imm16 positive values
lsh[b/w] imm4/imm6, reg ==> ashu[b/w] imm4/imm16, reg
- as CR16 core doesn't support lsh[b/w] right shift operaions. */
+ as CR16 core doesn't support lsh[b/w] right shift operations. */
if ((streq ("lshb", op) || streq ("lshw", op) || streq ("lshd", op))
&& (param [0] == '$'))
{
expressionS expr;
/* If there's an expression, we might need a relocation. Here's the
- type of what relocation to start relaxaton with.
+ type of what relocation to start relaxation with.
The relocation is assumed to start immediately after the prefix insn,
so we don't provide an offset. */
enum bfd_reloc_code_real reloc;
{
hashret = hash_insert (reg_hash, regtab->name, (void *) regtab);
if (hashret)
- as_fatal (_("Internal Error: Can't hash %s: %s"),
+ as_fatal (_("Internal error: Can't hash %s: %s"),
regtab->name,
hashret);
}
hashret = hash_insert (copreg_hash, copregtab->name,
(void *) copregtab);
if (hashret)
- as_fatal (_("Internal Error: Can't hash %s: %s"),
+ as_fatal (_("Internal error: Can't hash %s: %s"),
copregtab->name,
hashret);
}
static void
set_operand (char *operand, ins * crx_ins)
{
- char *operandS; /* Pointer to start of sub-opearand. */
- char *operandE; /* Pointer to end of sub-opearand. */
+ char *operandS; /* Pointer to start of sub-operand. */
+ char *operandE; /* Pointer to end of sub-operand. */
expressionS scale;
int scale_val;
char *input_save, c;
operandE++;
*operandE = '\0';
if ((cur_arg->r = get_register (operandS)) == nullregister)
- as_bad (_("Illegal register `%s' in Instruction `%s'"),
+ as_bad (_("Illegal register `%s' in instruction `%s'"),
operandS, ins_parse);
if (cur_arg->type != arg_rbase)
operandE++;
*operandE++ = '\0';
if ((cur_arg->r = get_register (operandS)) == nullregister)
- as_bad (_("Illegal register `%s' in Instruction `%s'"),
+ as_bad (_("Illegal register `%s' in instruction `%s'"),
operandS, ins_parse);
/* Skip leading white space. */
*operandE++ = '\0';
if ((cur_arg->i_r = get_register (operandS)) == nullregister)
- as_bad (_("Illegal register `%s' in Instruction `%s'"),
+ as_bad (_("Illegal register `%s' in instruction `%s'"),
operandS, ins_parse);
/* Skip leading white space. */
/* Issue a error message when register is illegal. */
#define IMAGE_ERR \
- as_bad (_("Illegal register (`%s') in Instruction: `%s'"), \
+ as_bad (_("Illegal register (`%s') in instruction: `%s'"), \
reg_name, ins_parse); \
break;
case arg_copr:
if (arg->cr < c0 || arg->cr > c15)
- as_bad (_("Illegal Co-processor register in Instruction `%s' "),
+ as_bad (_("Illegal co-processor register in instruction `%s'"),
ins_parse);
CRX_PRINT (0, getreg_image (arg->cr), shift);
break;
case arg_copsr:
if (arg->cr < cs0 || arg->cr > cs15)
- as_bad (_("Illegal Co-processor special register in Instruction `%s' "),
+ as_bad (_("Illegal co-processor special register in instruction `%s'"),
ins_parse);
CRX_PRINT (0, getreg_image (arg->cr), shift);
break;
else
/* Full match - print the encoding to output file. */
{
- /* Make further checkings (such that couldn't be made earlier).
+ /* Make further checking (such that couldn't be made earlier).
Warn the user if necessary. */
warn_if_needed (insn);
return 1;
}
-/* Bunch of error checkings.
+/* Bunch of error checking.
The checks are made after a matching instruction was found. */
void
{
if ((reg)r > (reg)sp)
{
- as_bad (_("Invalid Register in Register List"));
+ as_bad (_("Invalid register in register list"));
return;
}
int reg_counter = 0; /* Count number of parsed registers. */
unsigned short int mask = 0; /* Mask for 16 general purpose registers. */
char *new_param; /* New created operands string. */
- char *paramP = param; /* Pointer to original opearands string. */
+ char *paramP = param; /* Pointer to original operands string. */
char maskstring[10]; /* Array to print the mask as a string. */
int hi_found = 0, lo_found = 0; /* Boolean flags for hi/lo registers. */
reg r;
words[j++] = output_opcode[i] & 0xFFFF;
}
- /* Handle relaxtion. */
+ /* Handle relaxation. */
if ((instruction->flags & RELAXABLE) && relocatable)
{
int relax_subtype;
static struct hash_control *d10v_hash;
/* Do a binary search of the d10v_predefined_registers array to see if
- NAME is a valid regiter name. Return the register number from the
+ NAME is a valid register name. Return the register number from the
array on success, or -1 on failure. */
static int
static struct hash_control *d30v_hash;
/* Do a binary search of the pre_defined_registers array to see if
- NAME is a valid regiter name. Return the register number from the
+ NAME is a valid register name. Return the register number from the
array on success, or -1 on failure. */
static int
fprintf (stream, _("\nD30V options:\n\
-O Make adjacent short instructions parallel if possible.\n\
-n Warn about all NOPs inserted by the assembler.\n\
--N Warn about NOPs inserted after word multiplies.\n\
--c Warn about symbols whoes names match register names.\n\
+-N Warn about NOPs inserted after word multiplies.\n\
+-c Warn about symbols whose names match register names.\n\
-C Opposite of -C. -c is the default.\n"));
}
}
else if (prev_left_kills_right_p)
{
- /* The left instruction kils the right slot, so we
+ /* The left instruction kills the right slot, so we
must leave it empty. */
write_1_short (opcode1, insn1, fx->next, FALSE);
return 1;
/* Macro move operand/reg. */
if (operand->X_op == O_register)
{
- /* Its a register. */
+ /* It's a register. */
reg_shift = 21;
goto general_reg;
}
#define DISPMOD _("destination register modified by displacement-post-modified address")
#define LDSTODD _("ldrd/strd requires even:odd register pair")
- /* Helper macros for spliting apart instruction fields. */
+ /* Helper macros for splitting apart instruction fields. */
#define ADDR_POST_MODIFIED(i) (((i) >> 25) & 0x1)
#define ADDR_SIZE(i) (((i) >> 5) & 3)
#define ADDR_LOADSTORE(i) (((i) >> 4) & 0x1)
return FALSE;
/* Since we don't use partial_inplace, we must not reduce symbols in
- mergable sections to their section symbol. */
+ mergeable sections to their section symbol. */
if ((S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0)
return FALSE;
fprintf (stream, _("-mno-pack Do not allow instructions to be packed\n"));
fprintf (stream, _("-mpic Mark generated file as using small position independent code\n"));
fprintf (stream, _("-mPIC Mark generated file as using large position independent code\n"));
- fprintf (stream, _("-mlibrary-pic Mark generated file as using position indepedent code for libraries\n"));
+ fprintf (stream, _("-mlibrary-pic Mark generated file as using position independent code for libraries\n"));
fprintf (stream, _("-mfdpic Assemble for the FDPIC ABI\n"));
fprintf (stream, _("-mnopic Disable -mpic, -mPIC, -mlibrary-pic and -mfdpic\n"));
fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"));
#ifdef OBJ_ELF
/* ELF needs to mark the end of each function so that it can compute
- the size of the function (apparently its needed in the symbol table). */
+ the size of the function (apparently it's needed in the symbol table). */
hppa_elf_mark_end_of_function ();
#endif
(void) restore_line_pointer (c);
}
- /* If numeric, make sure its not out of bounds. */
+ /* If numeric, make sure it's not out of bounds. */
if ((0 <= reg_number) && (16 >= reg_number))
{
expressionP->X_op = O_register;
\f
/* Set i370_cpu if it is not already set.
Currently defaults to the reasonable superset;
- but can be made more fine grained if desred. */
+ but can be made more fine grained if desired. */
static void
i370_set_cpu (void)
\f
/* DC Define Const is only partially supported.
- For samplecode on what to do, look at i370_elf_cons() above.
+ For sample code on what to do, look at i370_elf_cons() above.
This code handles pseudoops of the style
DC D'3.141592653' # in sysv4, .double 3.14159265
DC F'1' # in sysv4, .long 1. */
start of each pool part.
lit_pool_num increments from zero to infinity and uniquely id's
- -- its used to generate the *_poolP symbol name. */
+ -- it's used to generate the *_poolP symbol name. */
#define MAX_LITERAL_POOL_SIZE 1024
/* The symbol setup for the literal pool is done in two steps. First,
a symbol that represents the start of the literal pool is created,
above, in the add_to_pool() routine. This sym ???_poolP.
- However, we don't know what fragment its in until a bit later.
+ However, we don't know what fragment it's in until a bit later.
So we defer the frag_now thing, and the symbol name, until .ltorg time. */
/* Can't use symbol_new here, so have to create a symbol and then at
- a later date assign it a value. Thats what these functions do. */
+ a later date assign it a value. That's what these functions do. */
static void
symbol_locate (symbolS *symbolP,
=X'AB' one byte
=X'abcd' two bytes
=X'000000AB' four bytes
- =XL4'AB' four bytes, left-padded withn zero. */
+ =XL4'AB' four bytes, left-padded with zero. */
if (('X' == name[0]) && (0 > cons_len))
{
save = input_line_pointer;
if (0 == strncmp (now_seg->name, ".text", 5))
{
if (iregno != i370_using_text_regno)
- as_bad (_("droping register %d in section %s does not match using register %d"),
+ as_bad (_("dropping register %d in section %s does not match using register %d"),
iregno, now_seg->name, i370_using_text_regno);
i370_using_text_regno = -1;
else
{
if (iregno != i370_using_other_regno)
- as_bad (_("droping register %d in section %s does not match using register %d"),
+ as_bad (_("dropping register %d in section %s does not match using register %d"),
iregno, now_seg->name, i370_using_other_regno);
if (i370_other_section != now_seg)
- as_bad (_("droping register %d in section %s previously used in section %s"),
+ as_bad (_("dropping register %d in section %s previously used in section %s"),
iregno, now_seg->name, i370_other_section->name);
i370_using_other_regno = -1;
}
/* Perform some off-by-one hacks on the length field of certain instructions.
- Its such a shame to have to do this, but the problem is that HLASM got
+ It's such a shame to have to do this, but the problem is that HLASM got
defined so that the lengths differ by one from the actual machine instructions.
- this code should probably be moved to a special inster-operand routine.
+ this code should probably be moved to a special inter-operand routine.
Sigh. Affected instructions are Compare Logical, Move and Exclusive OR
hack alert -- aren't *all* SS instructions affected ?? */
off_by_one = 0;
input_line_pointer = hold;
/* Perform some off-by-one hacks on the length field of certain instructions.
- Its such a shame to have to do this, but the problem is that HLASM got
+ It's such a shame to have to do this, but the problem is that HLASM got
defined so that the programmer specifies a length that is one greater
than what the machine instruction wants. Sigh. */
if (off_by_one && (0 == strcasecmp ("SS L", operand->name)))
if (size < 1 || size > 4)
abort ();
- printf (" gwana doo fixup %d \n", i);
+ printf (" gwana do fixup %d \n", i);
fixP = fix_new_exp (frag_now, f - frag_now->fr_literal, size,
&fixups[i].exp, reloc_howto->pc_relative,
fixups[i].reloc);
We are only prepared to turn a few of the operands into
relocs. In fact, we support *zero* operand relocations ...
Why? Because we are not expecting the compiler to generate
- any operands that need relocation. Due to the 12-bit naturew of
+ any operands that need relocation. Due to the 12-bit nature of
i370 addressing, this would be unusual. */
{
const char *sfile;
int has_offset; /* 1 if operand has offset. */
unsigned int in_offset; /* >=1 if processing operand of offset. */
unsigned int in_bracket; /* >=1 if processing operand in brackets. */
- unsigned int in_scale; /* >=1 if processing multipication operand
+ unsigned int in_scale; /* >=1 if processing multiplication operand
* in brackets. */
i386_operand_type reloc_types; /* Value obtained from lex_got(). */
const reg_entry *base; /* Base register (if any). */
/* 1 if register prefix % not required. */
static int allow_naked_reg = 0;
-/* 1 if the assembler should add BND prefix for all control-tranferring
+/* 1 if the assembler should add BND prefix for all control-transferring
instructions supporting it, even if this prefix wasn't specified
explicitly. */
static int add_bnd_prefix = 0;
if (*string == '.' && j >= ARRAY_SIZE (cpu_arch))
{
- /* Disable an ISA entension. */
+ /* Disable an ISA extension. */
for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
if (strcmp (string + 1, cpu_noarch [j].name) == 0)
{
else
register_specifier = 0xf;
- /* Use 2-byte VEX prefix by swappping destination and source
+ /* Use 2-byte VEX prefix by swapping destination and source
operand. */
if (!i.swap_operand
&& i.operands == i.reg_operands
continue;
break;
case 2:
- /* xchg %eax, %eax is a special case. It is an aliase for nop
+ /* xchg %eax, %eax is a special case. It is an alias for nop
only in 32bit mode and we can use opcode 0x90. In 64bit
mode, we can't use 0x90 for xchg %eax, %eax since it should
zero-extend %eax to %rax. */
if (i.tm.opcode_modifier.immext)
{
- /* When ImmExt is set, the immdiate byte is the last
+ /* When ImmExt is set, the immediate byte is the last
operand. */
imm_slot = i.operands - 1;
source--;
{
case BFD_RELOC_386_PLT32:
case BFD_RELOC_X86_64_PLT32:
- /* Symbol with PLT relocatin may be preempted. */
+ /* Symbol with PLT relocation may be preempted. */
return 0;
default:
abort ();
else if (*cpu_arch [j].name == '.'
&& strcmp (arch, cpu_arch [j].name + 1) == 0)
{
- /* ISA entension. */
+ /* ISA extension. */
i386_cpu_flags flags;
flags = cpu_flags_or (cpu_arch_flags,
if (j >= ARRAY_SIZE (cpu_arch))
{
- /* Disable an ISA entension. */
+ /* Disable an ISA extension. */
for (j = 0; j < ARRAY_SIZE (cpu_noarch); j++)
if (strcmp (arch, cpu_noarch [j].name) == 0)
{
of branches taken/not-taken for later input to a utility that will
set the branch prediction bits of the instructions in accordance with
the behavior observed. (Note that the KX series does not have
- brach-prediction.)
+ branch-prediction.)
The instrumentation consists of:
regnum = *intP;
*p = '\0'; /* Discard register spec. */
if (regnum == IPREL)
- /* We have to specialcase ip-rel mode. */
+ /* We have to special-case ip-rel mode. */
iprel_flag = 1;
else
{
n = 1;
args[1] = p;
- /* Squeze blanks out by moving non-blanks toward start of string.
+ /* Squeeze blanks out by moving non-blanks toward start of string.
Isolate operands, whenever comma is found. */
to = p;
while (*p != '\0')
if (!oP || !targ_has_iclass (oP->iclass))
as_bad (_("invalid opcode, \"%s\"."), args[0]);
else if (n_ops != oP->num_ops)
- as_bad (_("improper number of operands. expecting %d, got %d"),
+ as_bad (_("improper number of operands. Expecting %d, got %d"),
oP->num_ops, n_ops);
else
{
struct hash_control *const_hash; /* constant hash table */
struct hash_control *entry_hash; /* code entry hint hash table */
- /* If X_op is != O_absent, the registername for the instruction's
+ /* If X_op is != O_absent, the register name for the instruction's
qualifying predicate. If NULL, p0 is assumed for instructions
that are predictable. */
expressionS qp;
for (ptr = list; ptr; ptr = ptr->next)
{
if (ptr->slot_number == SLOT_NUM_NOT_SET)
- as_bad (_(" Insn slot not set in unwind record."));
+ as_bad (_("Insn slot not set in unwind record."));
t = slot_index (ptr->slot_number, ptr->slot_frag,
first_addr, first_frag, before_relax);
switch (ptr->r.type)
e2.X_op = O_absent;
reg1 = e1.X_add_number;
- /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
+ /* Make sure it's a valid ar.xxx reg, OR its br0, aka 'rp'. */
if (e1.X_op != O_register)
{
as_bad (_("First operand to .save not a register"));
reg1 = e1.X_add_number;
val = e2.X_add_number;
- /* Make sure its a valid ar.xxx reg, OR its br0, aka 'rp'. */
+ /* Make sure it's a valid ar.xxx reg, OR its br0, aka 'rp'. */
if (e1.X_op != O_register)
{
as_bad (_("First operand to .%s not a register"), po);
/* Non-zero if the programmer should not receive any messages about
parallel instruction with potential or real constraint violations.
The ability to suppress these messages is intended only for hardware
- vendors testing the chip. It superceedes
+ vendors testing the chip. It supersedes
warn_explicit_parallel_conflicts. */
static int ignore_parallel_conflicts = 0;
fprintf (stream, _("\
-warn-explicit-parallel-conflicts warn when parallel instructions\n"));
fprintf (stream, _("\
- might violate contraints\n"));
+ might violate constraints\n"));
fprintf (stream, _("\
-no-warn-explicit-parallel-conflicts do not warn when parallel\n"));
fprintf (stream, _("\
- instructions might violate contraints\n"));
+ instructions might violate constraints\n"));
fprintf (stream, _("\
-Wp synonym for -warn-explicit-parallel-conflicts\n"));
fprintf (stream, _("\
&& S_IS_DEFINED (fixP->fx_addsy)
&& ! S_IS_EXTERNAL(fixP->fx_addsy)
&& ! S_IS_WEAK(fixP->fx_addsy))
- /* Already used fx_offset in the opcode field itseld. */
+ /* Already used fx_offset in the opcode field itself. */
reloc->addend = fixP->fx_offset;
else
reloc->addend = fixP->fx_addnumber;
dbcc -> db!cc +3
jmp L
- Setting the flag forbidds this. */
+ Setting the flag forbids this. */
static short flag_fixed_branches = 0;
/* Force to use long jumps (absolute) instead of relative branches. */
{
#define OPTION_FORCE_LONG_BRANCH (OPTION_MD_BASE)
{"force-long-branches", no_argument, NULL, OPTION_FORCE_LONG_BRANCH},
- {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, /* Misspelt version kept for backwards compatibility. */
+ {"force-long-branchs", no_argument, NULL, OPTION_FORCE_LONG_BRANCH}, /* Misspelled version kept for backwards compatibility. */
#define OPTION_SHORT_BRANCHES (OPTION_MD_BASE + 1)
{"short-branches", no_argument, NULL, OPTION_SHORT_BRANCHES},
- {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHES}, /* Misspelt version kept for backwards compatibility. */
+ {"short-branchs", no_argument, NULL, OPTION_SHORT_BRANCHES}, /* Misspelled version kept for backwards compatibility. */
#define OPTION_STRICT_DIRECT_MODE (OPTION_MD_BASE + 2)
{"strict-direct-mode", no_argument, NULL, OPTION_STRICT_DIRECT_MODE},
}
/* XGATE Put a 1 byte expression described by 'oper'. If this expression
- containts unresolved symbols, generate an 8-bit fixup. */
+ contains unresolved symbols, generate an 8-bit fixup. */
static void
fixup8_xg (expressionS *oper, int mode, int opmode)
{
const relax_typeS *table = TC_GENERIC_RELAX_TABLE;
/* We only have to cope with frags as prepared by
- md_estimate_size_before_relax. The STATE_BITS16 case may geet here
+ md_estimate_size_before_relax. The STATE_BITS16 case may get here
because of the different reasons that it's not relaxable. */
switch (fragP->fr_subtype)
{
/* Pointer to list holding the opcodes sorted by name. */
static struct m68k_opcode const ** m68k_sorted_opcodes;
-/* Its an arbitrary name: This means I don't approve of it.
+/* It's an arbitrary name: This means I don't approve of it.
See flames below. */
static struct obstack robyn;
}
fragb[4];
- int nrel; /* Num of reloc strucs in use. */
+ int nrel; /* Num of reloc structs in use. */
struct
{
int n;
opsfound = opP - &the_ins.operands[0];
/* This ugly hack is to support the floating pt opcodes in their
- standard form. Essentially, we fake a first enty of type COP#1 */
+ standard form. Essentially, we fake a first entry of type COP#1 */
if (opcode->m_operands[0] == 'I')
{
int n;
int use_pl = 0;
/* This switch is a doozy.
- Watch the first step; its a big one! */
+ Watch the first step; it's a big one! */
switch (s[0])
{
default:
abort ();
}
- /* IF its simple,
+ /* IF it's simple,
GET US OUT OF HERE! */
/* Must be INDEX, with an index register. Address
}
}
- /* By the time whe get here (FINALLY) the_ins contains the complete
+ /* By the time when get here (FINALLY) the_ins contains the complete
instruction, ready to be emitted. . . */
}
switch (mode)
{
case '/': /* Special for mask loads for mac/msac insns with
- possible mask; trailing_ampersend set in bit 8. */
+ possible mask; trailing_ampersand set in bit 8. */
the_ins.opcode[0] |= (val & 0x3f);
the_ins.opcode[1] |= (((val & 0x100) >> 8) << 5);
break;
n = 4;
break;
default:
- as_fatal (_("Don't know how to figure width of %c in md_assemble()"),
+ as_fatal (_("Don't know how to figure out width of %c in md_assemble()"),
the_ins.reloc[m].wid);
}
#endif
-/* Different values of OK tell what its OK to return. Things that
+/* Different values of OK tell what it's OK to return. Things that
aren't OK are an error (what a shock, no?)
0: Everything is OK
"), default_cpu);
for (i = 0; m68k_extensions[i].name; i++)
fprintf (stream, _("\
--m[no-]%-16s enable/disable%s architecture extension\n\
+-m[no-]%-16s enable/disable %s architecture extension\n\
"), m68k_extensions[i].name,
m68k_extensions[i].alias > 0 ? " ColdFire"
: m68k_extensions[i].alias < 0 ? " m68k" : "");
kind == 2 means we just left a function
The dump_literals (1) call inserts a branch around the table, so
- we first look to see if its a situation where we won't have to
+ we first look to see if it's a situation where we won't have to
insert a branch (e.g., the previous instruction was an unconditional
branch).
case BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2:
/* Conditional linker map jsri to bsr. */
- /* If its a local target and close enough, fix it.
+ /* If it's a local target and close enough, fix it.
NB: >= -2k for backwards bsr; < 2k for forwards... */
if (fixP->fx_addsy == 0 && val >= -2048 && val < 2048)
{
void
md_operand (expressionS * expressionP)
{
- /* Ignore leading hash symbol, if poresent. */
+ /* Ignore leading hash symbol, if present. */
if (* input_line_pointer == '#')
{
input_line_pointer ++;
sized - maybe it will fix up */
fragP->fr_subtype = C (COND_JUMP, DISP12);
else if (fragP->fr_symbol)
- /* Its got a segment, but its not ours, so it will always be long. */
+ /* It's got a segment, but it's not ours, so it will always be long. */
fragP->fr_subtype = C (COND_JUMP, UNDEF_WORD_DISP);
else
/* We know the abs value. */
code = fixp->fx_r_type;
as_bad (_("Can not do %d byte %srelocation"),
fixp->fx_size,
- fixp->fx_pcrel ? _("pc-relative") : "");
+ fixp->fx_pcrel ? _("pc-relative ") : "");
}
break;
}
/* The MeP version of the cgen parse_operand function. The only difference
from the standard version is that we want to avoid treating '$foo' and
'($foo...)' as references to a symbol called '$foo'. The chances are
- that '$foo' is really a misspelt register. */
+ that '$foo' is really a misspelled register. */
static const char *
mep_parse_operand (CGEN_CPU_DESC cd, enum cgen_parse_operand_type want,
an internally parallel core or an internally parallel coprocessor,
neither of which are supported at this time. */
if ( num_insns_saved > 2 )
- as_fatal("Internally paralled cores and coprocessors not supported.");
+ as_fatal("Internally paralleled cores and coprocessors not supported.");
/* If there are no insns saved, that's ok. Just return. This will
happen when mep_process_saved_insns is called when the end of the
1. The instruction is a 32 bit core or coprocessor insn and
can be executed by itself. Valid.
- 2. The instrucion is a core instruction for which a cop nop
+ 2. The instruction is a core instruction for which a cop nop
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
mep_insn insn;
/* Move the insn and it's fixups to the second element of the
- saved insns arrary and insert a 16 bit core nope into the
+ saved insns array and insert a 16 bit core nope into the
first element. */
insn.insn = mep_cgen_assemble_insn (gas_cgen_cpu_desc, "nop",
&insn.fields, insn.buffer,
1. The instruction is a 64 bit coprocessor insn and can be
executed by itself. Valid.
- 2. The instrucion is a core instruction for which a cop nop
+ 2. The instruction is a core instruction for which a cop nop
exists. In this case, insert the cop nop into the saved
insn array after the core insn and return. Valid.
we have to abort. */
/* If the insn is 64 bits long, it can run alone. The size check
- is done indepependantly of whether the insn is core or copro
+ is done independently of whether the insn is core or copro
in case 64 bit coprocessor insns are added later. */
if (insn0length == 64)
return;
#endif /* MEP_IVC2_SUPPORTED */
/* The scheduling functions are just filters for invalid combinations.
- If there is a violation, they terminate assembly. Otherise they
+ If there is a violation, they terminate assembly. Otherwise they
just fall through. Successful combinations cause no side effects
other than valid nop insertion. */
break;
}
- /* Now call cgen's md_aply_fix. */
+ /* Now call cgen's md_apply_fix. */
gas_cgen_md_apply_fix (fixP, valP, seg);
}
/* The values of the following enum are for use with parinsnum, which
is a variable in md_assemble that keeps track of whether or not the
- next instruction is expected to be the first or second instrucion in
+ next instruction is expected to be the first or second instruction in
a parallelization group. */
typedef enum exp_par_insn_{FIRST, SECOND} EXP_PAR_INSN;
return NULL;
}
-/* Parse the immediate portion of an addrssing mode. */
+/* Parse the immediate portion of an addressing mode. */
static const char *
parse_imm_addr (const char *line, metag_addr *addr)
{
/* We don't entirely strip the register name because we might
actually want to match whole string in the register table,
e.g. "D0AW.1++" not just "D0AW.1". The string length of the table
- entry limits our comaprison to a reasonable bound anyway. */
+ entry limits our comparison to a reasonable bound anyway. */
while (is_register_char (*l) || *l == PLUS)
{
name[len] = *l;
insn->bits |= (1 << 2);
}
- /* Check for template definitons. */
+ /* Check for template definitions. */
if (IS_TEMPLATE_DEF (insn))
{
l = interpret_template_regs(l, insn, regs, regs_shift, &load,
int otype; /* Offset Type */
};
-/* These are NOT in assending order of type, GOTOFF is ahead to make
+/* These are NOT in ascending order of type, GOTOFF is ahead to make
sure @GOTOFF does not get matched with @GOT */
static struct imm_type imm_types[] = {
{ "NONE", IMM_NONE , 0 },
code = fixp->fx_r_type;
as_bad (_("Can not do %d byte %srelocation"),
fixp->fx_size,
- fixp->fx_pcrel ? _("pc-relative") : "");
+ fixp->fx_pcrel ? _("pc-relative ") : "");
}
break;
}
return FALSE;
if (offset_reloc[0] != BFD_RELOC_UNUSED)
- /* Relocation operators were used. Accept the arguent and
+ /* Relocation operators were used. Accept the argument and
leave the relocation value in offset_expr and offset_relocs
for the caller to process. */
return TRUE;
{
/* Search until we get a match for NAME. It is assumed here that
macros will never generate MDMX, MIPS-3D, or MT instructions.
- We try to match an instruction that fulfils the branch delay
+ We try to match an instruction that fulfills the branch delay
slot instruction length requirement (if any) of the previous
instruction. While doing this we record the first instruction
seen that matches all the other conditions and use it anyway
LOCAL is the sum of a symbol and a 16-bit or 32-bit displacement.
The two alternatives are:
- Global symbol Local sybmol
+ Global symbol Local symbol
------------- ------------
lw DEST,%got(SYMBOL) lw DEST,%got(SYMBOL + OFFSET)
... ...
is then identified by the section offset rather than by the symbol.
However, if we're generating REL LO16 relocations, the offset is split
- between the LO16 and parterning high part relocation. The linker will
+ between the LO16 and partnering high part relocation. The linker will
need to recalculate the complete offset in order to correctly identify
the merge data.
- The linker has traditionally not looked for the parterning high part
+ The linker has traditionally not looked for the partnering high part
relocation, and has thus allowed orphaned R_MIPS_LO16 relocations to be
placed anywhere. Rather than break backwards compatibility by changing
this, it seems better not to force the issue, and instead keep the
c = get_symbol_name (&p);
- /* Reseting prefix? */
+ /* Resetting prefix? */
if (*p == ':' && p[1] == 0)
mmix_current_prefix = NULL;
else
(sizeof (other_registers) / sizeof (struct reg_name))
/* reg_name_search does a binary search of the given register table
- to see if "name" is a valid regiter name. Returns the register
+ to see if "name" is a valid register name. Returns the register
number from the array on success, or -1 on failure. */
static int
#define OTHER_REG_NAME_CNT ARRAY_SIZE (other_registers)
/* Perform a binary search of the given register table REGS to see
- if NAME is a valid regiter name. Returns the register number from
+ if NAME is a valid register name. Returns the register number from
the array on success, or -1 on failure. */
static int
/* Likewise, do not adjust symbols that won't be merged, or debug
symbols, because they too break relaxation. We do want to adjust
- other mergable symbols, like .rodata, because code relaxations
+ other mergeable symbols, like .rodata, because code relaxations
need section-relative symbols to properly relax them. */
if (! (S_GET_SEGMENT (fixp->fx_addsy)->flags & SEC_MERGE))
return FALSE;
? BFD_RELOC_MSP430_16_BYTE : BFD_RELOC_MSP430_16))
/* Generate a 16-bit pc-relative relocation.
- For the 430X we generate a relocation without linkwer range checking.
+ For the 430X we generate a relocation without linker range checking.
For the 430 we generate a relocation without assembler range checking
if we are handling an immediate value or a byte-width instruction. */
#undef CHECK_RELOC_MSP430_PCREL
else
{
as_bad (_
- ("unknown expression in operand %s. use #llo() #lhi() #hlo() #hhi() "),
+ ("unknown expression in operand %s. Use #llo(), #lhi(), #hlo() or #hhi()"),
l);
return 1;
}
instruction that does not support it. Look for an alternative extended
instruction that has the same name without the period. Eg: "add.a"
becomes "adda". Although this not an officially supported way of
- specifing instruction aliases other MSP430 assemblers allow it. So we
+ specifying instruction aliases other MSP430 assemblers allow it. So we
support it for compatibility purposes. */
if (addr_op && opcode->fmt >= 0)
{
parse_exp (l1 + 1, &(op1.exp));
if (op1.exp.X_op != O_constant)
{
- as_bad (_("expected constant expression for first argument of %s"),
+ as_bad (_("expected constant expression as first argument of %s"),
opcode->name);
break;
}
parse_exp (l1 + 1, &(op1.exp));
if (op1.exp.X_op != O_constant)
{
- as_bad (_("expected constant expression for first argument of %s"),
+ as_bad (_("expected constant expression as first argument of %s"),
opcode->name);
break;
}
break;
default:
- as_bad (_("Illegal emulated instruction "));
+ as_bad (_("Illegal emulated instruction"));
break;
}
break;
if (x > 512 || x < -511)
{
- as_bad (_("Wrong displacement %d"), x << 1);
+ as_bad (_("Wrong displacement %d"), x << 1);
break;
}
if (!cmd[0])
{
- as_bad (_("can't find opcode "));
+ as_bad (_("can't find opcode"));
return;
}
because there can be multiple incarnations of the same label, with
exactly the same name, in any given section and the linker will have
no way to identify the correct one. Instead we just have to hope
- that no relaxtion will occur between the local label and the other
+ that no relaxation will occur between the local label and the other
symbol in the expression.
Similarly we have to compute differences between symbols in the .eh_frame
}
else if (fragP->fr_symbol)
{
- /* Its got a segment, but its not ours. Even if fr_symbol is in
+ /* It's got a segment, but it's not ours. Even if fr_symbol is in
an absolute segment, we don't know a displacement until we link
object files. So it will always be long. This also applies to
labels in a subsegment of current. Liker may relax it to short
break;
default:
- as_fatal (_("internal inconsistency problem in %s: %lx"),
+ as_fatal (_("internal inconsistency problem in %s: %lx"),
__FUNCTION__, (long) fragP->fr_subtype);
break;
}
#define tc_fix_adjustable(FIX) msp430_fix_adjustable (FIX)
extern bfd_boolean msp430_fix_adjustable (struct fix *);
-/* Allow hexadeciaml numbers with 'h' suffix. Note that if the number
+/* Allow hexadecimal numbers with 'h' suffix. Note that if the number
starts with a letter it will be interpreted as a symbol name not a
constant. Thus "beach" is a symbol not the hex value 0xbeac. So
is A5A5h... */
}
/* Set if label adjustment is needed. I should not adjust .xbyte in dwarf. */
-static symbolS *nds32_last_label; /* Last label for aligment. */
+static symbolS *nds32_last_label; /* Last label for alignment. */
-/* This code is referred from D30V for adjust label to be with pedning
- aligment. For example,
+/* This code is referred from D30V for adjust label to be with pending
+ alignment. For example,
LBYTE: .byte 0x12
LHALF: .half 0x12
LWORD: .word 0x12
- Without this, the above label will not attatch to incoming data. */
+ Without this, the above label will not attach to incoming data. */
static void
nds32_adjust_label (int n)
{
- /* FIXME: I think adjust lable and alignment is
- the programmer's obligation. Saddly, VLSI team doesn't
+ /* FIXME: I think adjust label and alignment is
+ the programmer's obligation. Sadly, VLSI team doesn't
properly use .align for their test cases.
So I re-implement cons_align and auto adjust labels, again.
- I think d30v's implmentation is simple and good enough. */
+ I think d30v's implementation is simple and good enough. */
symbolS *label = nds32_last_label;
nds32_last_label = NULL;
There are two things should be done for auto-adjust-label.
1. Align data/instructions and adjust label to be attached to them.
- 2. Clear auto-adjust state, so incommng data/instructions will not
+ 2. Clear auto-adjust state, so incoming data/instructions will not
adjust the label.
For example,
fragP = frag_now;
frag_align_code (n, max);
- /* Tag this alignment when there is a lable before it. */
+ /* Tag this alignment when there is a label before it. */
if (label_exist)
{
fragP->tc_frag_data.flag = NDS32_FRAG_LABEL;
asm_desc.parse_operand = nds32_asm_parse_operand;
nds32_asm_init (&asm_desc, 0);
- /* Initial general pupose registers hash table. */
+ /* Initial general purpose registers hash table. */
nds32_gprs_hash = hash_new ();
for (k = keyword_gpr; k->name; k++)
hash_insert (nds32_gprs_hash, k->name, k);
},
{
/* LONGJUMP5. */
- /* There is two kinds of veriation of LONGJUMP5. One of them
+ /* There is two kinds of variations of LONGJUMP5. One of them
generate EMPTY relocation for converted INSN16 if needed.
But we don't distinguish them here. */
_dummy_first_bfd_reloc_code_real,
if (map_ptr->insn_list == 0)
{
- as_warn (_("Can not find match relax hint. line : %d"),
+ as_warn (_("Can not find match relax hint. Line: %d"),
relocs_pattern->frag->fr_line);
return FALSE;
}
}
/* Clear final relocation. */
memset (hint_fixup, 0, sizeof (nds32_relax_fixup_info_t));
- /* Copy code sequance. */
+ /* Copy code sequence. */
memcpy (hint_code, code_seq, seq_size);
return TRUE;
}
if ((baseline_isa & attr) == 0)
{
- as_bad (_("Not support instrcution %s in the baseline."), str);
+ as_bad (_("Instruction %s not supported in the baseline."), str);
return FALSE;
}
return TRUE;
{
/* User assembly code branch relax for it. */
/* If fld is not NULL, it is a symbol. */
- /* Branch msut relax to proper pattern in user assembly code exclude
+ /* Branch must relax to proper pattern in user assembly code exclude
J and JAL. Keep these two in original type for users which wants
to keep their size be fixed. In general, assembler does not convert
instruction generated by compiler. But jump instruction may be
fragP->tc_frag_data.insn = insn.insn;
fragP->fr_fix += 2;
- /* In original, we don't relax the instrucion with label on it,
+ /* In original, we don't relax the instruction with label on it,
but this may cause some redundant nop16. Therefore, tag this
relaxable instruction and relax it carefully. */
if (label)
expressionS exp;
out = frag_var (rs_machine_dependent, insn.opcode->isize,
0, 0, NULL, 0, NULL);
- /* If this insturction is branch target, it is not relaxable. */
+ /* If this instruction is branch target, it is not relaxable. */
fragP->tc_frag_data.flag = NDS32_FRAG_LABEL;
fragP->tc_frag_data.opcode = insn.opcode;
fragP->tc_frag_data.insn = insn.insn;
return range_type;
}
-/* Set insntruction register mask. */
+/* Set instruction register mask. */
static void
nds32_elf_get_set_cond (relax_info_t *relax_info, int offset, uint32_t *insn,
if (fragP->fr_symbol == NULL)
return adjust;
- /* If frag_var is not enough room, the previos frag is fr_full and with
+ /* If frag_var is not enough room, the previous frag is fr_full and with
opcode. The new one is rs_dependent but without opcode. */
if (opcode == NULL)
return adjust;
|| frag_t->fr_type == rs_align_code
|| frag_t->fr_type == rs_align_test)
{
- /* Relax instruction can not walk across lable. */
+ /* Relax instruction can not walk across label. */
if (frag_t->tc_frag_data.flag & NDS32_FRAG_LABEL)
{
prev_frag = NULL;
return;
}
- /* Relax previos relaxable to align rs_align frag. */
+ /* Relax previous relaxable to align rs_align frag. */
address = frag_t->fr_address + frag_t->fr_fix;
addressT offset = nds32_get_align (address, (int) frag_t->fr_offset);
if (offset & 0x2)
if (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXABLE
&& (fragP->tc_frag_data.flag & NDS32_FRAG_RELAXED) == 0)
/* Here is considered relaxed case originally. But it may cause
- unendless loop when relaxing. Once the instruction is relaxed,
- it can not be undo. */
+ an endless loop when relaxing. Once the instruction is relaxed,
+ it can not be undone. */
prev_frag = fragP;
return adjust;
1. relax for branch
2. relax for 32-bits to 16-bits */
- /* Save previos relaxable frag. */
+ /* Save previous relaxable frag. */
static fragS *prev_frag = NULL;
int adjust = 0;
if (branch_symbol == NULL && !(fragP->tc_frag_data.flag & NDS32_FRAG_RELAXED))
return;
- /* If frag_var is not enough room, the previos frag is fr_full and with
+ /* If frag_var is not enough room, the previous frag is fr_full and with
opcode. The new one is rs_dependent but without opcode. */
if (opcode == NULL)
return;
origin_insn, branch_range_type);
/* Try to convert to 16-bits instruction. Currently, only the first
- insntruction in pattern can be converted. EX: bnez sethi ori jr,
+ instruction in pattern can be converted. EX: bnez sethi ori jr,
only bnez can be converted to 16 bit and ori can't. */
while (fixup_info[k].size != 0
else
{
/* These flags are only enabled when global relax is enabled.
- Maybe we can check DISABLE_RELAX_FLAG at linke-time,
+ Maybe we can check DISABLE_RELAX_FLAG at link-time,
so we set them anyway. */
if (enable_relax_ex9)
exp.X_add_number |= R_NDS32_RELAX_ENTRY_EX9_FLAG;
fixP->tc_fix_data = NULL;
/* Transform specific relocations here for later relocation generation.
- Tag data here for ex9 relaxtion and tag tls data for linker. */
+ Tag data here for ex9 relaxation and tag tls data for linker. */
switch (fixP->fx_r_type)
{
case BFD_RELOC_NDS32_DATA:
---- 8< ---- 8< ---- 8< ---- 8< ----
We use a single relocation entry for this expression.
- * The initial distance value is stored direcly in that location
+ * The initial distance value is stored directly in that location
specified by r_offset (i.e., foo in this example.)
* The begin of the region, i.e., .LBEGIN, is specified by
r_info/R_SYM and r_addend, e.g., .text + 0x32.
exprP->X_op = O_symbol;
exprP->X_add_number = 0;
- /* Check the specail name if a symbol. */
+ /* Check the special name if a symbol. */
segment = S_GET_SEGMENT (exprP->X_add_symbol);
if (segment != undefined_section)
return 0;
relax_substateT flag;
struct nds32_opcode *opcode;
uint32_t insn;
- /* To Save previos label fixup if existence. */
+ /* To Save previous label fixup if existence. */
struct fix *fixup;
};
/* The max relaxation pattern is 20-bytes including the nop. */
#define NDS32_MAXCHAR 20
-/* In current, the max entend number of instruction for one pseudo instruction
+/* In current, the max extended number of instruction for one pseudo instruction
is 4, but its number of relocation may be 12. */
#define MAX_RELAX_NUM 4
#define MAX_RELAX_FIX 12
#define CDX_CBRANCH_SUBTYPE(N) (CDXBRANCH | CBRANCH | (N))
#define SUBTYPE_ADDIS(SUBTYPE) ((SUBTYPE) & 0xffff)
-/* For the -relax-section mode, unconditional branches require 2 extra i
- nstructions besides the addis, conditional branches require 3. */
+/* For the -relax-section mode, unconditional branches require 2 extra
+ instructions besides the addis, conditional branches require 3. */
#define UBRANCH_ADDIS_TO_SIZE(N) (((N) + 2) * 4)
#define CBRANCH_ADDIS_TO_SIZE(N) (((N) + 3) * 4)
nios2_ps_insn_infoS *ps_insn;
- /* Find which real insn the pseudo-op transates to and
+ /* Find which real insn the pseudo-op translates to and
switch the insn_info ptr to point to it. */
ps_insn = nios2_ps_lookup (insn->insn_nios2_opcode->name);
separator characters are commas, brackets and space.
The instruction name is always separated from other tokens by a space
The maximum number of tokens in an instruction is 5 (the instruction name,
- 3 arguments, and a 4th string representing the expected instructin opcode
+ 3 arguments, and a 4th string representing the expected instruct in opcode
after assembly. The latter is only used when the assemble is running in
self test mode, otherwise its presence will generate an error. */
#define NIOS2_MAX_INSN_TOKENS 6
10 implied1
11 implied2
- For every entry there is a datalength in bytes. This is stored in size[n].
- 0, the objectlength is not explicitly given by the instruction
+ For every entry there is a data length in bytes. This is stored in size[n].
+ 0, the object length is not explicitly given by the instruction
and the operand is undefined. This is a case for relaxation.
Reserve 4 bytes for the final object.
The low-order-byte corresponds to low physical memory.
Obviously a FRAGment must be created for each valid disp in PART whose
- datalength is undefined (to bad) .
+ data length is undefined (to bad) .
The case where just the expression is undefined is less severe and is
- handled by fix. Here the number of bytes in the objectfile is known.
+ handled by fix. Here the number of bytes in the object file is known.
With this representation we simplify the assembly and separates the
machine dependent/independent parts in a more clean way (said OE). */
\f
char disp_size[] =
{4, 1, 2, 0, 4};
\f
-/* Parse a general operand into an addressingmode struct
+/* Parse a general operand into an addressing mode struct
In: pointer at operand in ascii form
pointer at addr_mode struct for result
addrmodeP->am_size += 1; /* scaled index byte. */
j = str[strl - 4] - '0'; /* store temporary. */
- str[strl - 6] = '\000'; /* nullterminate for recursive call. */
+ str[strl - 6] = '\000'; /* null terminate for recursive call. */
i = addr_mode (str, addrmodeP, 1);
if (!i || addrmodeP->mode == 20)
if ((tmp = addrmodeP->scaled_reg))
{ /* Build indexbyte. */
tmp--; /* Remember regnumber comes incremented for
- flagpurpose. */
+ flag purpose. */
tmp |= addrmodeP->scaled_mode << 3;
addrmodeP->index_byte = (char) tmp;
addrmodeP->am_size += 1;
return addrmodeP->mode;
}
-/* Read an optionlist. */
+/* Read an option list. */
static void
optlist (char *str, /* The string to extract options from. */
switch ((d = operandsP[(loop << 1) + 1]))
{
case 'f': /* Operand of sfsr turns out to be a nasty
- specialcase. */
+ special-case. */
opcode_bit_ptr -= 5;
/* Fall through. */
case 'Z': /* Float not immediate. */
opcode_bit_ptr -= 3;
iif.iifP[1].object |= tmp << opcode_bit_ptr;
break;
- case 'O': /* Setcfg instruction optionslist. */
+ case 'O': /* Setcfg instruction options list. */
optlist (argv[i], opt3, &tmp);
opcode_bit_ptr -= 4;
iif.iifP[1].object |= tmp << 15;
break;
- case 'C': /* Cinv instruction optionslist. */
+ case 'C': /* Cinv instruction options list. */
optlist (argv[i], opt4, &tmp);
opcode_bit_ptr -= 4;
iif.iifP[1].object |= tmp << 15; /* Insert the regtype in opcode. */
number_to_chars_littleendian (buf, value, nbytes);
}
-/* This is a variant of md_numbers_to_chars. The reason for its'
+/* This is a variant of md_numbers_to_chars. The reason for its
existence is the fact that ns32k uses Huffman coded
displacements. This implies that the bit order is reversed in
displacements and that they are prefixed with a size-tag.
break;
default:
- as_fatal (_("Internal logic error. line %d, file \"%s\""),
+ as_fatal (_("Internal logic error. Line %d, file: \"%s\""),
__LINE__, __FILE__);
}
}
arg += 3;
}
- /* Commersial instructions. */
+ /* Commercial instructions. */
if (strcmp (arg, "cis") == 0)
pdp11_extension[PDP11_CIS] = yes;
/* Call supervisor mode. */
{
/* On a PDP-11, 0x1234 is stored as "\x12\x34", and
0x12345678 is stored as "\x56\x78\x12\x34". It's
- anyones guess what 0x123456 would be stored like. */
+ anyone's guess what 0x123456 would be stored like. */
switch (nbytes)
{
{
/* On a PDP-11, 0x1234 is stored as "\x12\x34", and
0x12345678 is stored as "\x56\x78\x12\x34". It's
- anyones guess what 0x123456 would be stored like. */
+ anyone's guess what 0x123456 would be stored like. */
switch (nbytes)
{
case 0:
\n\
PDP-11 instruction set extensions:\n\
\n\
--m(no-)cis allow (disallow) commersial instruction set\n\
+-m(no-)cis allow (disallow) commercial instruction set\n\
-m(no-)csm allow (disallow) CSM instruction\n\
-m(no-)eis allow (disallow) full extended instruction set\n\
-m(no-)fis allow (disallow) KEV11 floating-point instructions\n\
-m(no-)ucode allow (disallow) microcode instructions\n\
-mall-extensions allow all instruction set extensions\n\
(this is the default)\n\
--mno-extentions disallow all instruction set extensions\n\
--pic generate position-indepenent code\n\
+-mno-extensions disallow all instruction set extensions\n\
+-pic generate position-independent code\n\
\n\
PDP-11 CPU model options:\n\
\n\
-mpower8, -mpwr8 generate code for Power8 architecture\n\
-mpower9, -mpwr9 generate code for Power9 architecture\n\
-mcell generate code for Cell Broadband Engine architecture\n\
--mcom generate code Power/PowerPC common instructions\n\
+-mcom generate code for Power/PowerPC common instructions\n\
-many generate code for any architecture (PWR/PWRX/PPC)\n"));
fprintf (stream, _("\
-maltivec generate code for AltiVec\n\
(In principle, there's no reason why the relocations _have_ to be at
the beginning. Anywhere in the csect would do. However, inserting
- at the beginning is what the native assmebler does, and it helps to
+ at the beginning is what the native assembler does, and it helps to
deal with cases where the .ref statements follow the section contents.)
??? .refs don't work for empty .csects. However, the native assembler
initial: .section .reldata "drw3"
d - initialized data
r - readable
- w - writeable
+ w - writable
3 - double word aligned (that would be 8 byte boundary)
commentary:
*
* Section Protection:
* 'r' - section is readable
- * 'w' - section is writeable
+ * 'w' - section is writable
* 'x' - section is executable
* 's' - section is sharable
*
* Section Alignment:
* '0' - align to byte boundary
- * '1' - align to halfword undary
+ * '1' - align to halfword boundary
* '2' - align to word boundary
* '3' - align to doubleword boundary
* '4' - align to quadword boundary
case 'r': /* section is readable */
flags |= IMAGE_SCN_MEM_READ;
break;
- case 'w': /* section is writeable */
+ case 'w': /* section is writable */
flags |= IMAGE_SCN_MEM_WRITE;
break;
case 'x': /* section is executable */
static int pru_auto_align_on = 1;
/* The last seen label in the current section. This is used to auto-align
- labels preceeding instructions. */
+ labels preceding instructions. */
static symbolS *pru_last_label;
\f
3. Try any directories specified by the -I command line
option(s).
- 4 .Try a directory specifed by the INC100 environment variable. */
+ 4 .Try a directory specified by the INC100 environment variable. */
if (IS_ABSOLUTE_PATH (f))
try = fopen (path = f, FOPEN_RT);
/* Estimate how big the opcode is after this relax pass. The return
value is the difference between fr_fix and the actual size. We
compute the total size in rx_relax_frag and store it in fr_subtype,
- sowe only need to subtract fx_fix and return it. */
+ so we only need to subtract fx_fix and return it. */
int
md_estimate_size_before_relax (fragS * fragP ATTRIBUTE_UNUSED, segT segment ATTRIBUTE_UNUSED)
}
}
-/* Test for @lit and if its present make an entry in the literal pool and
+/* Test for @lit and if it's present make an entry in the literal pool and
modify the current expression to be an offset into the literal pool. */
static elf_suffix_type
s390_lit_suffix (char **str_p, expressionS *exp_p, elf_suffix_type suffix)
}
/* Now change exp_p to the offset into the literal pool.
- Thats the expression: .L^Ax^By-.L^Ax */
+ That's the expression: .L^Ax^By-.L^Ax */
exp_p->X_add_symbol = lpe->sym;
exp_p->X_op_symbol = lp_sym;
exp_p->X_op = O_subtract;
if (*str != '(')
{
/* Check if parenthesized block can be skipped. If the next
- operand is neiter an optional operand nor a base register
+ operand is neither an optional operand nor a base register
then we have a syntax error. */
operand = s390_operands + *(++opindex_ptr);
if (!(operand->flags & (S390_OPERAND_INDEX|S390_OPERAND_BASE)))
operand = s390_operands + *(++opindex_ptr);
if (operand->flags & S390_OPERAND_OPTIONAL)
continue;
- as_bad (_("syntax error; expected ,"));
+ as_bad (_("syntax error; expected ','"));
break;
}
}
}
else if (operand->flags & S390_OPERAND_BASE)
{
- /* After the base register the parenthesed block ends. */
+ /* After the base register the parenthesised block ends. */
if (*str++ != ')')
as_bad (_("syntax error; missing ')' after base register"));
skip_optional = 0;
operand = s390_operands + *(++opindex_ptr);
if (operand->flags & S390_OPERAND_OPTIONAL)
continue;
- as_bad (_("syntax error; expected ,"));
+ as_bad (_("syntax error; expected ','"));
break;
}
}
operand = s390_operands + *(++opindex_ptr);
if (operand->flags & S390_OPERAND_OPTIONAL)
continue;
- as_bad (_("syntax error; expected ,"));
+ as_bad (_("syntax error; expected ','"));
break;
}
}
static const struct s3_insn_to_dependency s3_insn_to_dependency_table[] =
{
- /* move spectial instruction. */
+ /* move special instruction. */
{"mtcr", s3_D_mtcr},
};
static const struct s3_data_dependency s3_data_dependency_table[] =
{
- /* Status regiser. */
+ /* Status register. */
{s3_D_mtcr, "cr0", s3_D_all_insn, "", 5, 1, 0},
};
{
if ((reg == 1) && (s3_nor1 == 1) && (s3_inst.bwarn == 0))
{
- as_warn (_("Using temp register(r1)"));
+ as_warn (_("Using temp register (r1)"));
s3_inst.bwarn = 1;
}
}
/* Restore the start point, we may have got a reg of the wrong class. */
*str = start;
- sprintf (buff, _("low register(r0-r15)expected, not '%.100s'"), start);
+ sprintf (buff, _("low register (r0-r15) expected, not '%.100s'"), start);
s3_inst.error = buff;
return (int) s3_FAIL;
}
if (remainder_bubbles <= 2)
{
if (s3_warn_fix_data_dependency)
- as_warn (_("Fix data dependency: %s %s -- %s %s (insert %d nop!/%d)"),
+ as_warn (_("Fix data dependency: %s %s -- %s %s (insert %d nop!/%d)"),
s3_dependency_vector[i].name, s3_dependency_vector[i].reg,
s3_dependency_vector[0].name, s3_dependency_vector[0].reg,
remainder_bubbles, bubbles);
else
{
if (s3_warn_fix_data_dependency)
- as_warn (_("Fix data dependency: %s %s -- %s %s (insert 1 pflush/%d)"),
+ as_warn (_("Fix data dependency: %s %s -- %s %s (insert 1 pflush/%d)"),
s3_dependency_vector[i].name, s3_dependency_vector[i].reg,
s3_dependency_vector[0].name, s3_dependency_vector[0].reg,
bubbles);
{
if (warn_or_error)
{
- as_bad (_("data dependency: %s %s -- %s %s (%d/%d bubble)"),
+ as_bad (_("data dependency: %s %s -- %s %s (%d/%d bubble)"),
s3_dependency_vector[i].name, s3_dependency_vector[i].reg,
s3_dependency_vector[0].name, s3_dependency_vector[0].reg,
remainder_bubbles, bubbles);
}
else
{
- as_warn (_("data dependency: %s %s -- %s %s (%d/%d bubble)"),
+ as_warn (_("data dependency: %s %s -- %s %s (%d/%d bubble)"),
s3_dependency_vector[i].name, s3_dependency_vector[i].reg,
s3_dependency_vector[0].name, s3_dependency_vector[0].reg,
remainder_bubbles, bubbles);
/* Here, we must call frag_grow in order to keep the instruction frag type is
rs_machine_dependent.
For, frag_var may change frag_now->fr_type to rs_fill by calling frag_grow which
- acturally will call frag_wane.
+ actually will call frag_wane.
Calling frag_grow first will create a new frag_now which free size is 20 that is enough
for frag_var. */
frag_grow (20);
return;
/* 0: indicate 32.
- 1: invalide value.
+ 1: invalid value.
2: to 31: normal value. */
val = s3_inst.instruction & 0x1f;
if (val == 1)
return;
/* 0: indicate 32.
- 1: invalide value.
+ 1: invalid value.
2: to 31: normal value. */
val = s3_inst.instruction & 0x1f;
if (val == 1)
/* Var part
For a local symbol: ldis r1, HI%<constant>
- but, if lo is outof 16 bit, make hi plus 1 */
+ but, if lo is out of 16 bit, make hi plus 1 */
if ((lo < -0x8000) || (lo > 0x7fff))
{
hi += 1;
else if (!(s3_inst.reloc.exp.X_add_number >= -524288
&& s3_inst.reloc.exp.X_add_number <= 524287))
{
- s3_inst.error = _("invalid constant: 20 bit expression not in range -2^19..2^19");
+ s3_inst.error = _("invalid constant: 20 bit expression not in range -2^19..2^19-1");
return;
}
|| ((pec_part_1.size == s3_INSN_SIZE) && (s3_inst.size == s3_INSN16_SIZE))
|| ((pec_part_1.size == s3_INSN16_SIZE) && (s3_inst.size == s3_INSN_SIZE)))
{
- s3_inst.error = _("pce instruction error (16 bit || 16 bit)'");
+ s3_inst.error = _("pce instruction error (16 bit || 16 bit).");
sprintf (s3_inst.str, "%s", insnstr);
return;
}
if (change == 1)
{
/* Only at the first time determining whether s3_GP instruction relax should be done,
- return the difference between insntruction size and instruction relax size. */
+ return the difference between instruction size and instruction relax size. */
if (fragp->fr_opcode == NULL)
{
fragp->fr_fix = s3_RELAX_NEW (fragp->fr_subtype);
value = offset + symbol_address - frag_addr;
/* change the order of judging rule is because
- 1.not defined symbol or common sysbol or external symbol will change
+ 1.not defined symbol or common symbol or external symbol will change
bcmp to cmp!+beq/bne ,here need to record fragp->fr_opcode
2.if the flow is as before : it will results to recursive loop
*/
/* Have already relaxed! Just return 0 to terminate the loop. */
return 0;
}
- /* need to translate when extern or not defind or common sysbol */
+ /* need to translate when extern or not defined or common symbol */
else if ((relaxable_p
&& (!((value & 0xfffffe00) == 0 || (value & 0xfffffe00) == 0xfffffe00))
&& fragp->fr_fix == 4
if ((value & 0xfffffe00) != 0 && (value & 0xfffffe00) != 0xfffffe00)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- _(" branch relocation truncate (0x%x) [-2^9 ~ 2^9]"), (unsigned int)value);
+ _(" branch relocation truncate (0x%x) [-2^9 ~ 2^9-1]"), (unsigned int) value);
return;
}
content = s3_md_chars_to_number (buf, s3_INSN16_SIZE);
if ((value & 0xfff80000) != 0 && (value & 0xfff80000) != 0xfff80000)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- _(" branch relocation truncate (0x%x) [-2^19 ~ 2^19]"), (unsigned int)value);
+ _(" branch relocation truncate (0x%x) [-2^19 ~ 2^19-1]"), (unsigned int) value);
return;
}
content = s3_md_chars_to_number (buf, s3_INSN_SIZE);
if ((value & 0xfff80000) != 0 && (value & 0xfff80000) != 0xfff80000)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- _(" branch relocation truncate (0x%x) [-2^19 ~ 2^19]"), (unsigned int)value);
+ _(" branch relocation truncate (0x%x) [-2^19 ~ 2^19-1]"), (unsigned int) value);
return;
}
content = s3_md_chars_to_number (buf, s3_INSN_SIZE);
if ((value & 0xfffffe00) != 0 && (value & 0xfffffe00) != 0xfffffe00)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- _(" branch relocation truncate (0x%x) [-2^9 ~ 2^9]"), (unsigned int)value);
+ _(" branch relocation truncate (0x%x) [-2^9 ~ 2^9-1]"), (unsigned int) value);
return;
}
if ((value & 0xfff80000) != 0 && (value & 0xfff80000) != 0xfff80000)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- _(" branch relocation truncate (0x%x) [-2^19 ~ 2^19]"), (unsigned int)value);
+ _(" branch relocation truncate (0x%x) [-2^19 ~ 2^19-1]"), (unsigned int) value);
return;
}
if ((value & 0xfffffe00) != 0 && (value & 0xfffffe00) != 0xfffffe00)
{
as_bad_where (fixP->fx_file, fixP->fx_line,
- _(" branch relocation truncate (0x%x) [-2^9 ~ 2^9]"), (unsigned int)value);
+ _(" branch relocation truncate (0x%x) [-2^9 ~ 2^9-1]"), (unsigned int) value);
return;
}
#endif
fprintf (fp, _("\
- -FIXDD\t\tassemble code for fix data dependency\n"));
+ -FIXDD\t\tfix data dependencies\n"));
fprintf (fp, _("\
- -NWARN\t\tassemble code for no warning message for fix data dependency\n"));
+ -NWARN\t\tdo not print warning message when fixing data dependencies\n"));
fprintf (fp, _("\
- -SCORE5\t\tassemble code for target is SCORE5\n"));
+ -SCORE5\t\tassemble code for target SCORE5\n"));
fprintf (fp, _("\
- -SCORE5U\tassemble code for target is SCORE5U\n"));
+ -SCORE5U\tassemble code for target SCORE5U\n"));
fprintf (fp, _("\
- -SCORE7\t\tassemble code for target is SCORE7, this is default setting\n"));
+ -SCORE7\t\tassemble code for target SCORE7 [default]\n"));
fprintf (fp, _("\
- -SCORE3\t\tassemble code for target is SCORE3\n"));
+ -SCORE3\t\tassemble code for target SCORE3\n"));
fprintf (fp, _("\
- -march=score7\tassemble code for target is SCORE7, this is default setting\n"));
+ -march=score7\tassemble code for target SCORE7 [default]\n"));
fprintf (fp, _("\
- -march=score3\tassemble code for target is SCORE3\n"));
+ -march=score3\tassemble code for target SCORE3\n"));
fprintf (fp, _("\
-USE_R1\t\tassemble code for no warning message when using temp register r1\n"));
fprintf (fp, _("\
- -KPIC\t\tassemble code for PIC\n"));
+ -KPIC\t\tgenerate PIC\n"));
fprintf (fp, _("\
- -O0\t\tassembler will not perform any optimizations\n"));
+ -O0\t\tdo not perform any optimizations\n"));
fprintf (fp, _("\
- -G gpnum\tassemble code for setting gpsize and default is 8 byte\n"));
+ -G gpnum\tassemble code for setting gpsize, default is 8 bytes\n"));
fprintf (fp, _("\
- -V \t\tSunplus release version \n"));
+ -V \t\tSunplus release version\n"));
}
{"mvpl", s7_D_cond_mv},
{"mvvs", s7_D_cond_mv},
{"mvvc", s7_D_cond_mv},
- /* move spectial instruction. */
+ /* move special instruction. */
{"mtcr", s7_D_mtcr},
{"mftlb", s7_D_mftlb},
{"mtptlb", s7_D_mtptlb},
{s7_D_mtcr, "cr1", s7_D_pce, "", 2, 1, 0},
{s7_D_mtcr, "cr1", s7_D_cond_br, "", 1, 0, 1},
{s7_D_mtcr, "cr1", s7_D_cond_mv, "", 1, 0, 1},
- /* Status regiser. */
+ /* Status register. */
{s7_D_mtcr, "cr0", s7_D_all_insn, "", 5, 4, 0},
- /* CCR regiser. */
+ /* CCR register. */
{s7_D_mtcr, "cr4", s7_D_all_insn, "", 6, 5, 0},
/* EntryHi/EntryLo register. */
{s7_D_mftlb, "", s7_D_mtptlb, "", 1, 1, 1},
if (remainder_bubbles <= 2)
{
if (s7_warn_fix_data_dependency)
- as_warn (_("Fix data dependency: %s %s -- %s %s (insert %d nop!/%d)"),
+ as_warn (_("Fix data dependency: %s %s -- %s %s (insert %d nop!/%d)"),
s7_dependency_vector[i].name, s7_dependency_vector[i].reg,
s7_dependency_vector[0].name, s7_dependency_vector[0].reg,
remainder_bubbles, bubbles);
else
{
if (s7_warn_fix_data_dependency)
- as_warn (_("Fix data dependency: %s %s -- %s %s (insert 1 pflush/%d)"),
+ as_warn (_("Fix data dependency: %s %s -- %s %s (insert 1 pflush/%d)"),
s7_dependency_vector[i].name, s7_dependency_vector[i].reg,
s7_dependency_vector[0].name, s7_dependency_vector[0].reg,
bubbles);
{
if (warn_or_error)
{
- as_bad (_("data dependency: %s %s -- %s %s (%d/%d bubble)"),
+ as_bad (_("data dependency: %s %s -- %s %s (%d/%d bubble)"),
s7_dependency_vector[i].name, s7_dependency_vector[i].reg,
s7_dependency_vector[0].name, s7_dependency_vector[0].reg,
remainder_bubbles, bubbles);
}
else
{
- as_warn (_("data dependency: %s %s -- %s %s (%d/%d bubble)"),
+ as_warn (_("data dependency: %s %s -- %s %s (%d/%d bubble)"),
s7_dependency_vector[i].name, s7_dependency_vector[i].reg,
s7_dependency_vector[0].name, s7_dependency_vector[0].reg,
remainder_bubbles, bubbles);
/* Here, we must call frag_grow in order to keep the instruction frag type is
rs_machine_dependent.
For, frag_var may change frag_now->fr_type to rs_fill by calling frag_grow which
- acturally will call frag_wane.
+ actually will call frag_wane.
Calling frag_grow first will create a new frag_now which free size is 20 that is enough
for frag_var. */
frag_grow (20);
/* Var part
For a local symbol: ldis r1, HI%<constant>
- but, if lo is outof 16 bit, make hi plus 1 */
+ but, if lo is out of 16 bit, make hi plus 1 */
if ((lo < -0x8000) || (lo > 0x7fff))
{
hi += 1;
if (change == 1)
{
/* Only at the first time determining whether s7_GP instruction relax should be done,
- return the difference between insntruction size and instruction relax size. */
+ return the difference between instruction size and instruction relax size. */
if (fragp->fr_opcode == NULL)
{
fragp->fr_fix = s7_RELAX_NEW (fragp->fr_subtype);
grows -= 2;
do_relax_p = 1;
}
- /* Make the 32 bit insturction word align. */
+ /* Make the 32 bit instruction word align. */
else
{
fragp->insn_addr += 2;
\f
#ifdef OBJ_ELF
-/* Determinet whether the symbol needs any kind of PIC relocation. */
+/* Determine whether the symbol needs any kind of PIC relocation. */
inline static int
sh_PIC_related_p (symbolS *sym)
if (max != 0 && (val < min || val > max))
as_bad_where (fixP->fx_file, fixP->fx_line, _("offset out of range"));
else if (max != 0)
- /* Stop the generic code from trying to overlow check the value as well.
+ /* Stop the generic code from trying to overflow check the value as well.
It may not have the correct value anyway, as we do not store val back
into *valP. */
fixP->fx_no_overflow = 1;
}
else if (fragP->fr_symbol)
{
- /* Its got a segment, but its not ours, so it will always be long. */
+ /* It's got a segment, but it's not ours, so it will always be long. */
fragP->fr_subtype = C (what, UNDEF_WORD_DISP);
}
else
shmedia_md_pcrel_from_section (struct fix *fixP, segT sec ATTRIBUTE_UNUSED)
{
/* Use the ISA for the instruction to decide which offset to use. We
- can glean it from the fisup type. */
+ can glean it from the fixup type. */
switch (fixP->fx_r_type)
{
case BFD_RELOC_SH_IMM_LOW16:
p->pop = &pop_table[i];
}
- /* Last entry is the centinel. */
+ /* Last entry is the sentinel. */
perc_table[entry].type = perc_entry_none;
qsort (perc_table, sizeof (perc_table) / sizeof (perc_table[0]),
}
as_bad (_("Architecture mismatch on \"%s %s\"."), str, argsStart);
- as_tsktsk (_(" (Requires %s; requested architecture is %s.)"),
+ as_tsktsk (_("(Requires %s; requested architecture is %s.)"),
required_archs,
sparc_opcode_archs[max_architecture].name);
return special_case;
extern FLONUM_TYPE generic_floating_point_number;
/* Precision in LittleNums. */
-#define MAX_PRECISION (4) /* Its a bit overkill for us, but the code
+#define MAX_PRECISION (4) /* It's a bit overkill for us, but the code
requires it... */
#define S_PRECISION (1) /* Short float constants 16-bit. */
#define F_PRECISION (2) /* Float and double types 32-bit. */
as_bad (_("Non-constant symbols not allowed\n"));
return;
}
- exp.X_add_number &= 255; /* Limit numeber to 8-bit */
+ exp.X_add_number &= 255; /* Limit number to 8-bit */
emit_expr (&exp, 1);
bytes++;
}
static int assembly_begun = 0;
/* Addressing mode is not entirely implemented; the latest rev of the Other
assembler doesn't seem to make any distinction whatsoever; all relocations
- are stored as extended relocatiosn. Older versions used REL16 vs RELEXT16,
+ are stored as extended relocations. Older versions used REL16 vs RELEXT16,
but now it seems all relocations are RELEXT16. We use all RELEXT16.
The cpu version is kind of a waste of time as well. There is one
void
md_show_usage (FILE *stream)
{
- fprintf (stream, _("C54x-specific command line options:\n"));
+ fprintf (stream, _("C54x-specific command line options:\n"));
fprintf (stream, _("-mfar-mode | -mf Use extended addressing\n"));
fprintf (stream, _("-mcpu=<CPU version> Specify the CPU version\n"));
fprintf (stream, _("-merrors-to-file <filename>\n"));
fprintf (stream, _("-me <filename> Redirect errors to a file\n"));
}
-/* Output a single character (upper octect is zero). */
+/* Output a single character (upper octet is zero). */
static void
tic54x_emit_char (char c)
{
if (!tic54x_initialized_section (seg))
{
- as_bad (_("Current section is unitialized, "
+ as_bad (_("Current section is uninitialized, "
"section name required for .clink"));
ignore_rest_of_line ();
return;
len = get_absolute_expression ();
if (beg + len > strlen (value))
{
- as_bad (_("Invalid length (use 0 to %d"),
+ as_bad (_("Invalid length (use 0 to %d)"),
(int) strlen (value) - beg);
break;
}
static int machine = -1;
-/* Indiciates the target BFD architecture. */
+/* Indicates the target BFD architecture. */
enum bfd_architecture v850_target_arch = bfd_arch_v850_rh850;
const char * v850_target_format = "elf32-v850-rh850";
static flagword v850_e_flags = 0;
(sizeof (vector_registers) / sizeof (struct reg_name))
/* Do a binary search of the given register table to see if NAME is a
- valid regiter name. Return the register number from the array on
+ valid register name. Return the register number from the array on
success, or -1 on failure. */
static int
{ rX - rY, rZ }
etc
- and also parses constant expressions whoes bits indicate the
+ and also parses constant expressions whose bits indicate the
registers in the lists. The LSB in the expression refers to
the lowest numbered permissible register in the register list,
and so on upwards. System registers are considered to be very
skip_white_space ();
/* If the expression starts with a curly brace it is a register list.
- Otherwise it is a constant expression, whoes bits indicate which
+ Otherwise it is a constant expression, whose bits indicate which
registers are to be included in the list. */
if (*input_line_pointer != '{')
{
else if ((operand->flags & V850_OPERAND_CACHEOP) != 0)
{
if (!cacheop_name (&ex, TRUE))
- errmsg = _("invalid cache oparation name");
+ errmsg = _("invalid cache operation name");
}
else if ((operand->flags & V850_OPERAND_PREFOP) != 0)
{
if (!prefop_name (&ex, TRUE))
- errmsg = _("invalid pref oparation name");
+ errmsg = _("invalid pref operation name");
}
else if ((operand->flags & V850_OPERAND_VREG) != 0)
{
else
insn = bfd_getl16 ((unsigned char *) where);
- /* When inserting loop offets a backwards displacement
+ /* When inserting loop offsets a backwards displacement
is encoded as a positive value. */
if (operand->flags & V850_INVERSE_PCREL)
value = - value;
bbsc e4
bbcc e5
Always, you complement 0th bit to reverse condition.
- Always, 1-byte opcde, longword-address, byte-address, 1-byte-displacement
+ Always, 1-byte opcode, longword-address, byte-address, 1-byte-displacement
2c. J<cond> where cond tests low-order memory bit
length of byte,word,long.
default:
my_operand_length = 2;
- printf ("I dn't understand access width %c\n", mywidth);
+ printf ("I don't understand access width %c\n", mywidth);
break;
}
printf ("VAX assembler instruction operand: ");
|| operandP->vop_access == 'a')
{
if (operandP->vop_access == 'v')
- as_warn (_("Invalid operand: immediate value used as base address."));
+ as_warn (_("Invalid operand: immediate value used as base address."));
else
- as_warn (_("Invalid operand: immediate value used as address."));
+ as_warn (_("Invalid operand: immediate value used as address."));
/* gcc 2.6.3 is known to generate these in at least
one case. */
}
/* Look up mnemonic in opcode table, and get the code,
the instruction format, and the flags that indicate
- which family members support this mnenonic. */
+ which family members support this mnemonic. */
if (get_opcode (&opcode, &amode, &arch_flags, mnem) < 0)
{
- as_bad ("Unknown instruction mnenonic `%s'", mnem);
+ as_bad ("Unknown instruction mnemonic `%s'", mnem);
return;
}
break;
case mode_das:
- /* register := register * 5-bit imediate/register shift count
+ /* register := register * 5-bit immediate/register shift count
Example:
asl.l r1,r2,4 */
ans = parse_gen_reg (&str, &r1);
else if (strcasecmp (arg, "v3") == 0)
current_architecture = XGATE_V3;
else
- as_bad (_(" architecture variant invalid"));
+ as_bad (_("architecture variant invalid"));
break;
case OPTION_PRINT_INSN_SYNTAX:
-mlong use 32-bit int ABI\n\
-mshort-double use 32-bit double ABI\n\
-mlong-double use 64-bit double ABI (default)\n\
- --mxgate specify the processor variant[default %s]\n\
+ --mxgate specify the processor variant [default %s]\n\
--print-insn-syntax print the syntax of instruction in case of error\n\
--print-opcodes print the list of instructions with syntax\n\
--generate-example generate an example of each instruction"),
if (!opcode)
{
- as_bad (_("matching operands to opcode "));
+ as_bad (_("matching operands to opcode"));
xgate_print_syntax (opcode_handle->opc0[0]->name);
}
else if (opcode->size == 2)
if (!directive_state_stack)
{
- as_bad (_("unmatched end directive"));
+ as_bad (_("unmatched .end directive"));
*directive = directive_none;
return;
}
/* First, move the frag out of the literal section and
to the appropriate place. */
- /* Insert an aligmnent frag at start of pool. */
+ /* Insert an alignment frag at start of pool. */
if (literal_pool->fr_next->fr_type == rs_machine_dependent &&
literal_pool->fr_next->fr_subtype == RELAX_LITERAL_POOL_END)
{
-Fup\n\
\ttreat undocumented z80-instructions that do not work on R800 as errors\n\
-r800\t assemble for R800\n\n\
-Default: -z80 -ignore-undocument-instructions -warn-unportable-instructions.\n");
+Default: -z80 -ignore-undocumented-instructions -warn-unportable-instructions.\n");
}
static symbolS * zero;
return 0;
}
-/* Parse general expression, not loooking for indexed addressing. */
+/* Parse general expression, not looking for indexed addressing. */
static const char *
parse_exp_not_indexed (const char *s, expressionS *op)
{
fixP->fx_no_overflow = (-128 <= val && val < 128);
if (!fixP->fx_no_overflow)
as_bad_where (fixP->fx_file, fixP->fx_line,
- _("index offset out of range"));
+ _("index offset out of range"));
*p_lit++ = val;
fixP->fx_done = 1;
}
case CLASS_REG_WORD:
case CLASS_REG_LONG:
case CLASS_REG_QUAD:
- /* Insert bit mattern of right reg. */
+ /* Insert bit pattern of right reg. */
*output_ptr++ = reg[c & 0xf];
break;
case CLASS_DISP:
#include "as.h"
#include "te-vms.h"
-/* The purspose of the two alternate versions below is to have one that
+/* The purpose of the two alternate versions below is to have one that
works for native VMS and one that works on an NFS mounted filesystem
(Unix Server/VMS client). The main issue being to generate the special
VMS file timestamps for the debug info. */
op2 = get_opmatch (&initial_insn->t.operand_map, precond->opname2);
if (op2 == NULL)
as_fatal (_("opcode '%s': no bound opname '%s' "
- "for precondition in %s"),
+ "for precondition in '%s'"),
xtensa_opcode_name (isa, opcode),
precond->opname2, from_string);
}
orig_op = get_opmatch (&initial_insn->t.operand_map,
op->operand_name);
if (orig_op == NULL)
- as_fatal (_("opcode %s: unidentified operand '%s' in '%s'"),
+ as_fatal (_("opcode '%s': unidentified operand '%s' in '%s'"),
opcode_name, op->operand_name, to_string);
append_field_op (bi, op->operand_num, orig_op->operand_num);
}
orig_op = get_opmatch (&initial_insn->t.operand_map,
operand_arg_name);
if (orig_op == NULL)
- as_fatal (_("opcode %s: unidentified operand '%s' in '%s'"),
+ as_fatal (_("opcode '%s': unidentified operand '%s' in '%s'"),
opcode_name, op->operand_name, to_string);
append_user_fn_field_op (bi, op->operand_num,
typ, orig_op->operand_num);
}
else
- as_fatal (_("opcode %s: could not parse operand '%s' in '%s'"),
+ as_fatal (_("opcode '%s': could not parse operand '%s' in '%s'"),
opcode_name, op->operand_name, to_string);
}
}
@subsection @code{.cfi_adjust_cfa_offset @var{offset}}
Same as @code{.cfi_def_cfa_offset} but @var{offset} is a relative
-value that is added/substracted from the previous offset.
+value that is added/subtracted from the previous offset.
@subsection @code{.cfi_offset @var{register}, @var{offset}}
Previous value of @var{register} is saved at offset @var{offset} from
@ifset Z80
The syntax for @code{equ} on the Z80 is
@samp{@var{symbol} equ @var{expression}}.
-On the Z80 it is an eror if @var{symbol} is already defined,
+On the Z80 it is an error if @var{symbol} is already defined,
but the symbol is not protected from later redefinition.
Compare @ref{Equiv}.
@end ifset
The two @code{exception_code} invocations above would create the
@code{.text.exception} and @code{.init.exception} sections respectively.
-This is useful e.g. to discriminate between anciliary sections that are
-tied to setup code to be discarded after use from anciliary sections that
+This is useful e.g. to discriminate between ancillary sections that are
+tied to setup code to be discarded after use from ancillary sections that
need to stay resident without having to define multiple @code{exception_code}
macros just for that purpose.
@item STT_TLS
@itemx tls_object
-Mark the symbol as being a thead-local data object.
+Mark the symbol as being a thread-local data object.
@item STT_COMMON
@itemx common
@code{simd} (Advanced SIMD Extensions for v8-A architecture, implies @code{fp}),
@code{virt} (Virtualization Extensions for v7-A architecture, implies
@code{idiv}),
-@code{pan} (Priviliged Access Never Extensions for v8-A architecture),
+@code{pan} (Privileged Access Never Extensions for v8-A architecture),
@code{ras} (Reliability, Availability and Serviceability extensions
for v8-A architecture),
@code{rdma} (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
interworking is not going to be performed. The presence of this
directive also implies @code{.thumb}
-This directive is not neccessary when generating EABI objects. On these
+This directive is not necessary when generating EABI objects. On these
targets the encoding is implicit when generating Thumb code.
@cindex @code{.thumb_set} directive, ARM
@cindex @code{.unwind_raw} directive, ARM
@item .unwind_raw @var{offset}, @var{byte1}, @dots{}
-Insert one of more arbitary unwind opcode bytes, which are known to adjust
+Insert one of more arbitrary unwind opcode bytes, which are known to adjust
the stack pointer by @var{offset} bytes.
For example @code{.unwind_raw 4, 0xb1, 0x01} is equivalent to
@node HPPA Notes
@section Notes
-As a back end for @sc{gnu} @sc{cc} @code{@value{AS}} has been throughly tested and should
+As a back end for @sc{gnu} @sc{cc} @code{@value{AS}} has been thoroughly tested and should
work extremely well. We have tested it only minimally on hand written assembly
code and no one has tested it much on the assembly output from the HP
compilers.
Since @samp{$} has no special meaning, you may use it in symbol names.
Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6.
-By using thesse symbolic names, @code{@value{AS}} can detect simple
+By using these symbolic names, @code{@value{AS}} can detect simple
syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca
for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base
for r3 and rpgt or r.pgt for r4.
@cindex @samp{-mnaked-reg} option, i386
@cindex @samp{-mnaked-reg} option, x86-64
@item -mnaked-reg
-This opetion specifies that registers don't require a @samp{%} prefix.
+This option specifies that registers don't require a @samp{%} prefix.
The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
@cindex @samp{-madd-bnd-prefix} option, i386
@cindex options, M32R
@cindex M32R options
-The Renease M32R version of @code{@value{AS}} has a few machine
+The Renesas M32R version of @code{@value{AS}} has a few machine
dependent options:
@table @code
@item -EB
@cindex @code{-EB} option, M32R
-This is a synonum for @emph{-big}.
+This is a synonym for @emph{-big}.
@item -KPIC
@cindex @code{-KPIC} option, M32R
@cindex directives, M32R
@cindex M32R directives
-The Renease M32R version of @code{@value{AS}} has a few architecture
+The Renesas M32R version of @code{@value{AS}} has a few architecture
specific directives:
@table @code
@item Instructions share the same execution pipeline
This message is produced when the assembler encounters a parallel
-instruction whoes components both use the same execution pipeline.
+instruction whose components both use the same execution pipeline.
@item Instructions write to the same destination register.
This message is produced when the assembler encounters a parallel
@cindex @code{cpu} directive, M680x0
@item .cpu @var{name}
-Select the target cpu. Valid valuse
+Select the target cpu. Valid values
for @var{name} are the same as for the @option{-mcpu} command line
option. This directive cannot be specified after
any instructions have been assembled. If it is given multiple times,
be expanded. It needs to be kept in mind that @code{mmixal} is both an
assembler and linker, while @code{@value{AS}} will expand instructions
that at link stage can be contracted. (Though linker relaxation isn't yet
-implemented in @code{@value{LD}}.) The option @samp{-x} also imples
+implemented in @code{@value{LD}}.) The option @samp{-x} also implies
@samp{--linker-allocated-gregs}.
@cindex @samp{--no-pushj-stubs} command line option, MMIX
@item -my
tells the assembler to generate a warning message if a NOP does not
-immediately forllow an instruction that enables or disables
+immediately follow an instruction that enables or disables
interrupts. This is the default.
Note that this option can be stacked with the @option{-mn} option so
The NDS32 processors family includes high-performance and low-power 32-bit
processors for high-end to low-end. @sc{gnu} @code{@value{AS}} for NDS32
architectures supports NDS32 ISA version 3. For detail about NDS32
-instruction set, please see the AndeStar ISA User Manual which is availible
+instruction set, please see the AndeStar ISA User Manual which is available
at http://www.andestech.com/en/index/index.htm
@menu
@section Options
The 32x32 version of @code{@value{AS}} accepts a @samp{-m32032} option to
-specify thiat it is compiling for a 32032 processor, or a
+specify that it is compiling for a 32032 processor, or a
@samp{-m32532} to specify that it is compiling for a 32532 option.
The default (if neither is specified) is chosen when the assembler
is compiled.
@node RISC-V-Opts
@section Options
-The following table lists all availiable RISC-V specific options
+The following table lists all available RISC-V specific options
@c man begin OPTIONS
@table @gcctabopt
@cindex options, RX
@cindex RX options
-The Renesas RX port of @code{@value{AS}} has a few target specfic
+The Renesas RX port of @code{@value{AS}} has a few target specific
command line options:
@table @code
@end display
There are many exceptions to the scheme outlined in the above lists, in
-particular for the priviledged instructions. For non-priviledged
+particular for the privileged instructions. For non-privileged
instruction it works quite well, for example the instruction @samp{clgfr}
c: compare instruction, l: unsigned operands, g: 64-bit operands,
f: 32- to 64-bit extension, r: register operands. The instruction compares
base register and the displacement field Dn.
@item Dn(Ln,Bn)
the address for operand number n is formed from the content of general
-regiser Bn called the base register and the displacement field Dn.
+register Bn called the base register and the displacement field Dn.
The length of the operand n is specified by the field Ln.
@end table
into double quotes in case it contains characters not appropriate
for identifiers. So you have to write @code{"z9-109"} instead of
just @code{z9-109}. Extensions can be specified after the cpu
-name, separated by plus charaters. Valid extensions are:
+name, separated by plus characters. Valid extensions are:
@code{htm},
@code{nohtm},
@code{vx},
@cindex @code{.endp} directive, TIC6X
@item .endp
-Marks the end of and exception table or function. If preceeded by a
+Marks the end of and exception table or function. If preceded by a
@code{.handlerdata} directive then this also switched back to the previous
text section.
@item tls_gd_call
-This modifier is used to tag an instrution as the ``call'' part of a
+This modifier is used to tag an instruction as the ``call'' part of a
calling sequence for a TLS GD reference of its operand.
@item tls_gd_add
@item tls_gd_call
-This modifier is used to tag an instrution as the ``call'' part of a
+This modifier is used to tag an instruction as the ``call'' part of a
calling sequence for a TLS GD reference of its operand.
@item tls_gd_add
@cindex @code{sdaoff} pseudo-op, V850
@item sdaoff()
Computes the offset of the named variable from the start of the Small
-Data Area (whoes address is held in register 4, the GP register) and
+Data Area (whose address is held in register 4, the GP register) and
stores the result as a 16 bit signed value in the immediate operand
field of the given instruction. For example:
@cindex @code{tdaoff} pseudo-op, V850
@item tdaoff()
Computes the offset of the named variable from the start of the Tiny
-Data Area (whoes address is held in register 30, the EP register) and
+Data Area (whose address is held in register 30, the EP register) and
stores the result as a 4,5, 7 or 8 bit unsigned value in the immediate
operand field of the given instruction. For example:
@cindex @code{ctoff} pseudo-op, V850
@item ctoff()
Computes the offset of the named variable from the start of the Call
-Table Area (whoes address is helg in system register 20, the CTBP
+Table Area (whose address is held in system register 20, the CTBP
register) and stores the result a 6 or 16 bit unsigned value in the
immediate field of then given instruction or piece of data. For
example:
@samp{callt ctoff(table_func1)}
-will put the call the function whoes address is held in the call table
+will put the call the function whose address is held in the call table
at the location labeled 'table_func1'.
@cindex @code{longcall} pseudo-op, V850
@end table
-Convience macro opcodes to deal with 16-bit values have been added.
+Convene macro opcodes to deal with 16-bit values have been added.
@table @dfn
@end group
@end smallexample
-The Xtensa assempler uses trampolines with jump around only when it cannot
+The Xtensa assembler uses trampolines with jump around only when it cannot
find suitable unreachable trampoline. There may be multiple trampolines
between the jump instruction and its target.
# define DWARF2_USE_FIXED_ADVANCE_PC linkrelax
#endif
-/* First special line opcde - leave room for the standard opcodes.
+/* First special line opcode - leave room for the standard opcodes.
Note: If you want to change this, you'll have to update the
"standard_opcode_lengths" table that is emitted below in
out_debug_line(). */
Each file table has offsets for where the line numbers, local
strings, local symbols, and procedure table starts from within the
- global tables, and the indexs are reset to 0 for each of those
+ global tables, and the indices are reset to 0 for each of those
tables for the file.
The procedure table contains the binary equivalents of the .ent
{
if (! stabs_seen)
{
- /* Add a dummy @stabs dymbol. */
+ /* Add a dummy @stabs symbol. */
stabs_seen = 1;
(void) add_ecoff_symbol (stabs_symbol, st_Nil, sc_Info,
(symbolS *) NULL,
struct itbl_entry {
e_processor processor; /* processor number */
e_type type; /* dreg/creg/greg/insn */
- char *name; /* mnemionic name for insn/register */
+ char *name; /* mnemonic name for insn/register */
unsigned long value; /* opcode/instruction mask/register number */
unsigned long flags; /* effects of the instruction */
struct itbl_range range; /* bit range within instruction for value */
ASSERT (size >= 0);
DBG (("I get=%d\n", size / sizeof (ITBL_OPCODES[0])));
- /* FIXME since ITBL_OPCODES culd be a static table,
+ /* FIXME since ITBL_OPCODES could be a static table,
we can't realloc or delete the old memory. */
new_opcodes = XNEWVEC (struct ITBL_OPCODE_STRUCT, new_num_opcodes);
if (!new_opcodes)
will affect the page they are on, as well as any subsequent page
.eject
- Thow a page
+ Throw a page
.list
Increment the enable listing counter
.nolist
}
else
{
- /* Permit macro parameter substition delineated with
+ /* Permit macro parameter substitution delineated with
an '&' prefix and optional '&' suffix. */
src = sub_actual (src + 1, in, &t, formal_hash, '&', out, 0);
}
free_macro (macro);
}
else
- as_warn (_("Attempt to purge non-existant macro `%s'"), copy);
+ as_warn (_("Attempt to purge non-existing macro `%s'"), copy);
free (copy);
}
"possible.\n"
"-n Warn about all NOPs inserted by the assembler.\n"
"-N\t\t\tWarn about NOPs inserted after word multiplies.\n"
-"-c Warn about symbols whoes names match register "
+"-c Warn about symbols whose names match register "
"names.\n"
"-C Opposite of -C. -c is the default.\n"
msgstr ""
02110-1301, USA. */
/* If your chars aren't 8 bits, you will change this a bit (eg. to 0xFF).
- But then, GNU isn't spozed to run on your machine anyway.
+ But then, GNU isn't supposed to run on your machine anyway.
(RMS is so shortsighted sometimes.) */
#define MASK_CHAR ((int)(unsigned char) -1)
}
/* Like do_repeat except that any text matching EXPANDER in the
- block is replaced by the itteration count. */
+ block is replaced by the iteration count. */
void
do_repeat_with_expander (int count,
struct symbol_flags
{
- /* Wether the symbol is a local_symbol. */
+ /* Whether the symbol is a local_symbol. */
unsigned int sy_local_symbol : 1;
- /* Wether symbol has been written. */
+ /* Weather symbol has been written. */
unsigned int sy_written : 1;
/* Whether symbol value has been completely resolved (used during
struct broken_word *use_jump;
};
extern struct broken_word *broken_words;
-#endif /* ndef WORKING_DOT_WORD */
+#endif /* ifdef WORKING_DOT_WORD */
/*
* Current means for getting from symbols to segments and vice verse.
[^:]*: Assembler messages:
-[^:]*:1: Error: Unable to use @plt relocatio for insn j
-[^:]*:2: Error: Unable to use @plt relocatio for insn jl
-[^:]*:3: Error: Unable to use @plt relocatio for insn j
+[^:]*:1: Error: Unable to use @plt relocation for insn j
+[^:]*:2: Error: Unable to use @plt relocation for insn jl
+[^:]*:3: Error: Unable to use @plt relocation for insn j
[^:]*:5: Error: Unable to use @pcl relocation for insn j
[^:]*:6: Error: Unable to use @pcl relocation for insn jl
[^:]*:7: Error: Unable to use @pcl relocation for insn j
Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
02110-1301, USA. */
-/* This thing should be set up to do byteordering correctly. But... */
+/* This thing should be set up to do byte ordering correctly. But... */
#include "as.h"
#include "subsegs.h"
projects / external / binutils.git / commitdiff