// We have target-specific dag combine patterns for the following nodes:
setTargetDAGCombine(ISD::TRUNCATE);
setTargetDAGCombine(ISD::SELECT);
+ setTargetDAGCombine(ISD::SELECT_CC);
// Set function alignment to 16 bytes
setMinFunctionAlignment(Align(16));
switch ((VEISD::NodeType)Opcode) {
case VEISD::FIRST_NUMBER:
break;
+ TARGET_NODE_CASE(CMPI)
+ TARGET_NODE_CASE(CMPU)
+ TARGET_NODE_CASE(CMPF)
+ TARGET_NODE_CASE(CMPQ)
TARGET_NODE_CASE(CMOV)
TARGET_NODE_CASE(CALL)
TARGET_NODE_CASE(EH_SJLJ_LONGJMP)
}
}
+static bool isSimm7(SDValue V) {
+ EVT VT = V.getValueType();
+ if (VT.isVector())
+ return false;
+
+ if (VT.isInteger()) {
+ if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(V))
+ return isInt<7>(C->getSExtValue());
+ } else if (VT.isFloatingPoint()) {
+ if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(V)) {
+ if (VT == MVT::f32 || VT == MVT::f64) {
+ const APInt &Imm = C->getValueAPF().bitcastToAPInt();
+ uint64_t Val = Imm.getSExtValue();
+ if (Imm.getBitWidth() == 32)
+ Val <<= 32; // Immediate value of float place at higher bits on VE.
+ return isInt<7>(Val);
+ }
+ }
+ }
+ return false;
+}
+
static bool isMImm(SDValue V) {
EVT VT = V.getValueType();
if (VT.isVector())
return false;
}
+static unsigned decideComp(EVT SrcVT, ISD::CondCode CC) {
+ if (SrcVT.isFloatingPoint()) {
+ if (SrcVT == MVT::f128)
+ return VEISD::CMPQ;
+ return VEISD::CMPF;
+ }
+ return isSignedIntSetCC(CC) ? VEISD::CMPI : VEISD::CMPU;
+}
+
+static EVT decideCompType(EVT SrcVT) {
+ if (SrcVT == MVT::f128)
+ return MVT::f64;
+ return SrcVT;
+}
+
+static bool safeWithoutCompWithNull(EVT SrcVT, ISD::CondCode CC,
+ bool WithCMov) {
+ if (SrcVT.isFloatingPoint()) {
+ // For the case of floating point setcc, only unordered comparison
+ // or general comparison with -enable-no-nans-fp-math option reach
+ // here, so it is safe even if values are NaN. Only f128 doesn't
+ // safe since VE uses f64 result of f128 comparison.
+ return SrcVT != MVT::f128;
+ }
+ if (isIntEqualitySetCC(CC)) {
+ // For the case of equal or not equal, it is safe without comparison with 0.
+ return true;
+ }
+ if (WithCMov) {
+ // For the case of integer setcc with cmov, all signed comparison with 0
+ // are safe.
+ return isSignedIntSetCC(CC);
+ }
+ // For the case of integer setcc, only signed 64 bits comparison is safe.
+ // For unsigned, "CMPU 0x80000000, 0" has to be greater than 0, but it becomes
+ // less than 0 witout CMPU. For 32 bits, other half of 32 bits are
+ // uncoditional, so it is not safe too without CMPI..
+ return isSignedIntSetCC(CC) && SrcVT == MVT::i64;
+}
+
+static SDValue generateComparison(EVT VT, SDValue LHS, SDValue RHS,
+ ISD::CondCode CC, bool WithCMov,
+ const SDLoc &DL, SelectionDAG &DAG) {
+ // Compare values. If RHS is 0 and it is safe to calculate without
+ // comparison, we don't generate an instruction for comparison.
+ EVT CompVT = decideCompType(VT);
+ if (CompVT == VT && safeWithoutCompWithNull(VT, CC, WithCMov) &&
+ (isNullConstant(RHS) || isNullFPConstant(RHS))) {
+ return LHS;
+ }
+ return DAG.getNode(decideComp(VT, CC), DL, CompVT, LHS, RHS);
+}
+
SDValue VETargetLowering::combineSelect(SDNode *N,
DAGCombinerInfo &DCI) const {
assert(N->getOpcode() == ISD::SELECT &&
return DAG.getNode(VEISD::CMOV, DL, VT, Ops);
}
+SDValue VETargetLowering::combineSelectCC(SDNode *N,
+ DAGCombinerInfo &DCI) const {
+ assert(N->getOpcode() == ISD::SELECT_CC &&
+ "Should be called with a SELECT_CC node");
+ ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
+ SDValue True = N->getOperand(2);
+ SDValue False = N->getOperand(3);
+
+ // We handle only scalar SELECT_CC.
+ EVT VT = N->getValueType(0);
+ if (VT.isVector())
+ return SDValue();
+
+ // Peform combineSelectCC after leagalize DAG.
+ if (!DCI.isAfterLegalizeDAG())
+ return SDValue();
+
+ // We handle only i32/i64/f32/f64/f128 comparisons.
+ EVT LHSVT = LHS.getValueType();
+ assert(LHSVT == RHS.getValueType());
+ switch (LHSVT.getSimpleVT().SimpleTy) {
+ case MVT::i32:
+ case MVT::i64:
+ case MVT::f32:
+ case MVT::f64:
+ case MVT::f128:
+ break;
+ default:
+ // Return SDValue to let llvm handle other types.
+ return SDValue();
+ }
+
+ if (isMImm(RHS)) {
+ // VE's comparison can handle MImm in RHS, so nothing to do.
+ } else if (isSimm7(RHS)) {
+ // VE's comparison can handle Simm7 in LHS, so swap LHS and RHS, and
+ // update condition code.
+ std::swap(LHS, RHS);
+ CC = getSetCCSwappedOperands(CC);
+ }
+ if (isMImm(True)) {
+ // VE's condition move can handle MImm in True clause, so nothing to do.
+ } else if (isMImm(False)) {
+ // VE's condition move can handle MImm in True clause, so swap True and
+ // False clauses if False has MImm value. And, update condition code.
+ std::swap(True, False);
+ CC = getSetCCInverse(CC, LHSVT);
+ }
+
+ SDLoc DL(N);
+ SelectionDAG &DAG = DCI.DAG;
+
+ bool WithCMov = true;
+ SDValue CompNode = generateComparison(LHSVT, LHS, RHS, CC, WithCMov, DL, DAG);
+
+ VECC::CondCode VECCVal;
+ if (LHSVT.isFloatingPoint()) {
+ VECCVal = fpCondCode2Fcc(CC);
+ } else {
+ VECCVal = intCondCode2Icc(CC);
+ }
+ SDValue Ops[] = {CompNode, True, False,
+ DAG.getConstant(VECCVal, DL, MVT::i32)};
+ return DAG.getNode(VEISD::CMOV, DL, VT, Ops);
+}
+
static bool isI32InsnAllUses(const SDNode *User, const SDNode *N);
static bool isI32Insn(const SDNode *User, const SDNode *N) {
switch (User->getOpcode()) {
case ISD::BITCAST:
case ISD::ATOMIC_CMP_SWAP:
case ISD::ATOMIC_SWAP:
+ case VEISD::CMPU:
+ case VEISD::CMPI:
return true;
case ISD::SRL:
if (N->getOperand(0).getOpcode() != ISD::SRL)
break;
case ISD::SELECT:
return combineSelect(N, DCI);
+ case ISD::SELECT_CC:
+ return combineSelectCC(N, DCI);
case ISD::TRUNCATE:
return combineTRUNCATE(N, DCI);
}
enum NodeType : unsigned {
FIRST_NUMBER = ISD::BUILTIN_OP_END,
+ CMPI, // Compare between two signed integer values.
+ CMPU, // Compare between two unsigned integer values.
+ CMPF, // Compare between two floating-point values.
+ CMPQ, // Compare between two quad floating-point values.
CMOV, // Select between two values using the result of comparison.
CALL, // A call instruction.
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
SDValue combineSelect(SDNode *N, DAGCombinerInfo &DCI) const;
+ SDValue combineSelectCC(SDNode *N, DAGCombinerInfo &DCI) const;
SDValue combineTRUNCATE(SDNode *N, DAGCombinerInfo &DCI) const;
/// } Custom DAGCombine
def getGOT : Operand<iPTR>;
+// Comparisons
+def cmpi : SDNode<"VEISD::CMPI", SDTIntBinOp>;
+def cmpu : SDNode<"VEISD::CMPU", SDTIntBinOp>;
+def cmpf : SDNode<"VEISD::CMPF", SDTFPBinOp>;
+def SDT_Cmpq : SDTypeProfile<1, 2, [SDTCisSameAs<1, 2>, SDTCisFP<0>,
+ SDTCisFP<2>]>;
+def cmpq : SDNode<"VEISD::CMPQ", SDT_Cmpq>;
+
// res = cmov cmp, t, f, cond
def SDT_Cmov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>,
SDTCisVT<4, i32>]>;
let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
// Section 8.4.14 - CMP (Compare)
-defm CMPUL : RRNCm<"cmpu.l", 0x55, I64, i64>;
-let cx = 1 in defm CMPUW : RRNCm<"cmpu.w", 0x55, I32, i32>;
+defm CMPUL : RRNCm<"cmpu.l", 0x55, I64, i64, cmpu>;
+let cx = 1 in defm CMPUW : RRNCm<"cmpu.w", 0x55, I32, i32, cmpu>;
// Section 8.4.15 - CPS (Compare Single)
defm CMPSWSX : RRNCm<"cmps.w.sx", 0x7A, I32, i32>;
-let cx = 1 in defm CMPSWZX : RRNCm<"cmps.w.zx", 0x7A, I32, i32>;
+let cx = 1 in defm CMPSWZX : RRNCm<"cmps.w.zx", 0x7A, I32, i32, cmpi>;
// Section 8.4.16 - CPX (Compare)
-defm CMPSL : RRNCm<"cmps.l", 0x6A, I64, i64>;
+defm CMPSL : RRNCm<"cmps.l", 0x6A, I64, i64, cmpi>;
// Section 8.4.17 - CMS (Compare and Select Maximum/Minimum Single)
// cx: sx/zx, cw: max/min
defm FDIVS : RRFm<"fdiv.s", 0x5D, F32, f32, fdiv, simm7fp, mimmfp32>;
// Section 8.7.5 - FCP (Floating Compare)
-defm FCMPD : RRFm<"fcmp.d", 0x7E, I64, f64>;
+defm FCMPD : RRFm<"fcmp.d", 0x7E, I64, f64, cmpf>;
let cx = 1 in
-defm FCMPS : RRFm<"fcmp.s", 0x7E, F32, f32, null_frag, simm7fp, mimmfp32>;
+defm FCMPS : RRFm<"fcmp.s", 0x7E, F32, f32, cmpf, simm7fp, mimmfp32>;
// Section 8.7.6 - CMS (Compare and Select Maximum/Minimum Single)
// cx: double/float, cw: max/min
defm FMULQ : RRFm<"fmul.q", 0x6D, F128, f128, fmul>;
// Section 8.7.10 - FCQ (Floating Compare Quadruple)
-defm FCMPQ : RRNCbm<"fcmp.q", 0x7D, I64, f64, F128, f128, null_frag, simm7fp,
+defm FCMPQ : RRNCbm<"fcmp.q", 0x7D, I64, f64, F128, f128, cmpq, simm7fp,
mimmfp>;
// Section 8.7.11 - FIX (Convert to Fixed Point)
def : Pat<(i32 (setcc f128:$l, f128:$r, cond:$cond)),
(setccrr<CMOVDrm> (fcond2cc $cond), (FCMPQrr $l, $r))>;
-// Helper classes to construct cmov patterns for the ease.
-//
-// Hiding INSERT_SUBREG/EXTRACT_SUBREG patterns.
-
-class cmovrr<Instruction INSN> :
- OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f),
- (INSN $cond, $comp, $t, $f)>;
-class cmovrm<Instruction INSN, SDNodeXForm MOP = MIMM> :
- OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f),
- (INSN $cond, $comp, (MOP $t), $f)>;
-class cmov32rr<Instruction INSN, SubRegIndex sub_oty> :
- OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f),
- (EXTRACT_SUBREG
- (INSN $cond, $comp,
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_oty),
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_oty)),
- sub_oty)>;
-class cmov32rm<Instruction INSN, SubRegIndex sub_oty, SDNodeXForm MOP = MIMM> :
- OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f),
- (EXTRACT_SUBREG
- (INSN $cond, $comp,
- (MOP $t),
- (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_oty)),
- sub_oty)>;
-class cmov128rr<Instruction INSN> :
- OutPatFrag<(ops node:$cond, node:$comp, node:$t, node:$f),
- (INSERT_SUBREG
- (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
- (INSN $cond, $comp,
- (EXTRACT_SUBREG $t, sub_odd),
- (EXTRACT_SUBREG $f, sub_odd)), sub_odd),
- (INSN $cond, $comp,
- (EXTRACT_SUBREG $t, sub_even),
- (EXTRACT_SUBREG $f, sub_even)), sub_even)>;
-
-// Generic SELECTCC pattern matches
-//
-// CMP %tmp, %l, %r ; compare %l and %r
-// or %res, %f, (0)1 ; initialize by %f
-// CMOV %res, %t, %tmp ; set %t if %tmp is true
-
-def : Pat<(i32 (selectcc i32:$l, i32:$r, i32:$t, i32:$f, CCSIOp:$cond)),
- (cmov32rr<CMOVWrr, sub_i32> (icond2cc $cond), (CMPSWSXrr $l, $r),
- $t, $f)>;
-def : Pat<(i32 (selectcc i32:$l, i32:$r, i32:$t, i32:$f, CCUIOp:$cond)),
- (cmov32rr<CMOVWrr, sub_i32> (icond2cc $cond), (CMPUWrr $l, $r),
- $t, $f)>;
-def : Pat<(i32 (selectcc i64:$l, i64:$r, i32:$t, i32:$f, CCSIOp:$cond)),
- (cmov32rr<CMOVLrr, sub_i32> (icond2cc $cond), (CMPSLrr $l, $r),
- $t, $f)>;
-def : Pat<(i32 (selectcc i64:$l, i64:$r, i32:$t, i32:$f, CCUIOp:$cond)),
- (cmov32rr<CMOVLrr, sub_i32> (icond2cc $cond), (CMPULrr $l, $r),
- $t, $f)>;
-def : Pat<(i32 (selectcc f32:$l, f32:$r, i32:$t, i32:$f, cond:$cond)),
- (cmov32rr<CMOVSrr, sub_i32> (fcond2cc $cond), (FCMPSrr $l, $r),
- $t, $f)>;
-def : Pat<(i32 (selectcc f64:$l, f64:$r, i32:$t, i32:$f, cond:$cond)),
- (cmov32rr<CMOVDrr, sub_i32> (fcond2cc $cond), (FCMPDrr $l, $r),
- $t, $f)>;
-def : Pat<(i32 (selectcc f128:$l, f128:$r, i32:$t, i32:$f, cond:$cond)),
- (cmov32rr<CMOVDrr, sub_i32> (fcond2cc $cond), (FCMPQrr $l, $r),
- $t, $f)>;
-
-def : Pat<(i64 (selectcc i32:$l, i32:$r, i64:$t, i64:$f, CCSIOp:$cond)),
- (cmovrr<CMOVWrr> (icond2cc $cond), (CMPSWSXrr $l, $r), $t, $f)>;
-def : Pat<(i64 (selectcc i32:$l, i32:$r, i64:$t, i64:$f, CCUIOp:$cond)),
- (cmovrr<CMOVWrr> (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>;
-def : Pat<(i64 (selectcc i64:$l, i64:$r, i64:$t, i64:$f, CCSIOp:$cond)),
- (cmovrr<CMOVLrr> (icond2cc $cond), (CMPSLrr $l, $r), $t, $f)>;
-def : Pat<(i64 (selectcc i64:$l, i64:$r, i64:$t, i64:$f, CCUIOp:$cond)),
- (cmovrr<CMOVLrr> (icond2cc $cond), (CMPULrr $l, $r), $t, $f)>;
-def : Pat<(i64 (selectcc f32:$l, f32:$r, i64:$t, i64:$f, cond:$cond)),
- (cmovrr<CMOVSrr> (fcond2cc $cond), (FCMPSrr $l, $r), $t, $f)>;
-def : Pat<(i64 (selectcc f64:$l, f64:$r, i64:$t, i64:$f, cond:$cond)),
- (cmovrr<CMOVDrr> (fcond2cc $cond), (FCMPDrr $l, $r), $t, $f)>;
-def : Pat<(i64 (selectcc f128:$l, f128:$r, i64:$t, i64:$f, cond:$cond)),
- (cmovrr<CMOVDrr> (fcond2cc $cond), (FCMPQrr $l, $r), $t, $f)>;
-
-def : Pat<(f32 (selectcc i32:$l, i32:$r, f32:$t, f32:$f, CCSIOp:$cond)),
- (cmov32rr<CMOVWrr, sub_f32> (icond2cc $cond), (CMPSWSXrr $l, $r),
- $t, $f)>;
-def : Pat<(f32 (selectcc i32:$l, i32:$r, f32:$t, f32:$f, CCUIOp:$cond)),
- (cmov32rr<CMOVWrr, sub_f32> (icond2cc $cond), (CMPUWrr $l, $r),
- $t, $f)>;
-def : Pat<(f32 (selectcc i64:$l, i64:$r, f32:$t, f32:$f, CCSIOp:$cond)),
- (cmov32rr<CMOVLrr, sub_f32> (icond2cc $cond), (CMPSLrr $l, $r),
- $t, $f)>;
-def : Pat<(f32 (selectcc i64:$l, i64:$r, f32:$t, f32:$f, CCUIOp:$cond)),
- (cmov32rr<CMOVLrr, sub_f32> (icond2cc $cond), (CMPULrr $l, $r),
- $t, $f)>;
-def : Pat<(f32 (selectcc f32:$l, f32:$r, f32:$t, f32:$f, cond:$cond)),
- (cmov32rr<CMOVSrr, sub_f32> (fcond2cc $cond), (FCMPSrr $l, $r),
- $t, $f)>;
-def : Pat<(f32 (selectcc f64:$l, f64:$r, f32:$t, f32:$f, cond:$cond)),
- (cmov32rr<CMOVDrr, sub_f32> (fcond2cc $cond), (FCMPDrr $l, $r),
- $t, $f)>;
-def : Pat<(f32 (selectcc f128:$l, f128:$r, f32:$t, f32:$f, cond:$cond)),
- (cmov32rr<CMOVDrr, sub_f32> (fcond2cc $cond), (FCMPQrr $l, $r),
- $t, $f)>;
-
-def : Pat<(f64 (selectcc i32:$l, i32:$r, f64:$t, f64:$f, CCSIOp:$cond)),
- (cmovrr<CMOVWrr> (icond2cc $cond), (CMPSWSXrr $l, $r), $t, $f)>;
-def : Pat<(f64 (selectcc i32:$l, i32:$r, f64:$t, f64:$f, CCUIOp:$cond)),
- (cmovrr<CMOVWrr> (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>;
-def : Pat<(f64 (selectcc i64:$l, i64:$r, f64:$t, f64:$f, CCSIOp:$cond)),
- (cmovrr<CMOVLrr> (icond2cc $cond), (CMPSLrr $l, $r), $t, $f)>;
-def : Pat<(f64 (selectcc i64:$l, i64:$r, f64:$t, f64:$f, CCUIOp:$cond)),
- (cmovrr<CMOVLrr> (icond2cc $cond), (CMPULrr $l, $r), $t, $f)>;
-def : Pat<(f64 (selectcc f32:$l, f32:$r, f64:$t, f64:$f, cond:$cond)),
- (cmovrr<CMOVSrr> (fcond2cc $cond), (FCMPSrr $l, $r), $t, $f)>;
-def : Pat<(f64 (selectcc f64:$l, f64:$r, f64:$t, f64:$f, cond:$cond)),
- (cmovrr<CMOVDrr> (fcond2cc $cond), (FCMPDrr $l, $r), $t, $f)>;
-def : Pat<(f64 (selectcc f128:$l, f128:$r, f64:$t, f64:$f, cond:$cond)),
- (cmovrr<CMOVDrr> (fcond2cc $cond), (FCMPQrr $l, $r), $t, $f)>;
-
-def : Pat<(f128 (selectcc i32:$l, i32:$r, f128:$t, f128:$f, CCSIOp:$cond)),
- (cmov128rr<CMOVWrr> (icond2cc $cond), (CMPSWSXrr $l, $r), $t, $f)>;
-def : Pat<(f128 (selectcc i32:$l, i32:$r, f128:$t, f128:$f, CCUIOp:$cond)),
- (cmov128rr<CMOVWrr> (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>;
-def : Pat<(f128 (selectcc i64:$l, i64:$r, f128:$t, f128:$f, CCSIOp:$cond)),
- (cmov128rr<CMOVLrr> (icond2cc $cond), (CMPSLrr $l, $r), $t, $f)>;
-def : Pat<(f128 (selectcc i64:$l, i64:$r, f128:$t, f128:$f, CCUIOp:$cond)),
- (cmov128rr<CMOVLrr> (icond2cc $cond), (CMPULrr $l, $r), $t, $f)>;
-def : Pat<(f128 (selectcc f32:$l, f32:$r, f128:$t, f128:$f, cond:$cond)),
- (cmov128rr<CMOVSrr> (fcond2cc $cond), (FCMPSrr $l, $r), $t, $f)>;
-def : Pat<(f128 (selectcc f64:$l, f64:$r, f128:$t, f128:$f, cond:$cond)),
- (cmov128rr<CMOVDrr> (fcond2cc $cond), (FCMPDrr $l, $r), $t, $f)>;
-def : Pat<(f128 (selectcc f128:$l, f128:$r, f128:$t, f128:$f, cond:$cond)),
- (cmov128rr<CMOVDrr> (fcond2cc $cond), (FCMPQrr $l, $r), $t, $f)>;
-
// Generic CMOV pattern matches
// CMOV accepts i64 $t, $f, and result. So, we extend it to support
// i32/f32/f64/f128 $t, $f, and result.
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, i@hi(, %s0)
; CHECK-NEXT: ldl.sx %s1, (, %s0)
-; CHECK-NEXT: or %s2, 1, (0)1
; CHECK-NEXT: .LBB8_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: or %s3, 0, %s1
-; CHECK-NEXT: cmpu.w %s4, %s1, %s2
-; CHECK-NEXT: or %s1, 1, (0)1
-; CHECK-NEXT: cmov.w.gt %s1, %s3, %s4
-; CHECK-NEXT: cas.w %s1, (%s0), %s3
-; CHECK-NEXT: brne.w %s1, %s3, .LBB8_1
+; CHECK-NEXT: or %s2, 0, %s1
+; CHECK-NEXT: cmpu.w %s3, %s1, (63)0
+; CHECK-NEXT: or %s1, 0, %s2
+; CHECK-NEXT: cmov.w.le %s1, (63)0, %s3
+; CHECK-NEXT: cas.w %s1, (%s0), %s2
+; CHECK-NEXT: brne.w %s1, %s2, .LBB8_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: fencem 3
; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: lea.sl %s0, i@hi(, %s0)
; CHECK-NEXT: ldl.sx %s1, (, %s0)
-; CHECK-NEXT: or %s2, 2, (0)1
; CHECK-NEXT: .LBB9_1: # %atomicrmw.start
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: or %s3, 0, %s1
-; CHECK-NEXT: cmpu.w %s4, %s1, %s2
-; CHECK-NEXT: or %s1, 1, (0)1
-; CHECK-NEXT: cmov.w.lt %s1, %s3, %s4
-; CHECK-NEXT: cas.w %s1, (%s0), %s3
-; CHECK-NEXT: brne.w %s1, %s3, .LBB9_1
+; CHECK-NEXT: or %s2, 0, %s1
+; CHECK-NEXT: cmpu.w %s3, 2, %s1
+; CHECK-NEXT: or %s1, 0, %s2
+; CHECK-NEXT: cmov.w.le %s1, (63)0, %s3
+; CHECK-NEXT: cas.w %s1, (%s0), %s2
+; CHECK-NEXT: brne.w %s1, %s2, .LBB9_1
; CHECK-NEXT: # %bb.2: # %atomicrmw.end
; CHECK-NEXT: adds.w.sx %s0, %s1, (0)1
; CHECK-NEXT: fencem 3
; CHECK-LABEL: br_cc_i128_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s2, 0, (0)1
-; CHECK-NEXT: cmps.l %s1, %s1, (0)1
-; CHECK-NEXT: or %s3, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s1
+; CHECK-NEXT: cmps.l %s3, %s1, (0)1
+; CHECK-NEXT: or %s4, 0, (0)1
+; CHECK-NEXT: cmov.l.gt %s4, (63)0, %s3
; CHECK-NEXT: cmpu.l %s0, %s0, (58)0
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: cmov.l.eq %s4, %s2, %s1
+; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
; CHECK-LABEL: br_cc_u128_imm:
; CHECK: # %bb.0:
; CHECK-NEXT: or %s2, 0, (0)1
-; CHECK-NEXT: cmps.l %s1, %s1, (0)1
-; CHECK-NEXT: or %s3, 0, (0)1
-; CHECK-NEXT: cmov.l.ne %s3, (63)0, %s1
+; CHECK-NEXT: cmps.l %s3, %s1, (0)1
+; CHECK-NEXT: or %s4, 0, (0)1
+; CHECK-NEXT: cmov.l.ne %s4, (63)0, %s3
; CHECK-NEXT: cmpu.l %s0, %s0, (58)0
; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: cmov.l.eq %s4, %s2, %s1
+; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
define void @br_cc_imm_i128(i128 %0) {
; CHECK-LABEL: br_cc_imm_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s1, %s1, (0)0
-; CHECK-NEXT: or %s2, 0, (0)1
+; CHECK-NEXT: cmps.l %s2, %s1, (0)0
; CHECK-NEXT: or %s3, 0, (0)1
-; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s1
+; CHECK-NEXT: or %s4, 0, (0)1
+; CHECK-NEXT: cmov.l.lt %s4, (63)0, %s2
; CHECK-NEXT: cmpu.l %s0, %s0, (58)1
-; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
+; CHECK-NEXT: cmpu.l %s0, %s1, (0)0
+; CHECK-NEXT: cmov.l.eq %s4, %s3, %s0
+; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
define void @br_cc_imm_u128(i128 %0) {
; CHECK-LABEL: br_cc_imm_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s1, %s1, (0)0
-; CHECK-NEXT: or %s2, 0, (0)1
+; CHECK-NEXT: cmps.l %s2, %s1, (0)0
; CHECK-NEXT: or %s3, 0, (0)1
-; CHECK-NEXT: cmov.l.ne %s3, (63)0, %s1
+; CHECK-NEXT: or %s4, 0, (0)1
+; CHECK-NEXT: cmov.l.ne %s4, (63)0, %s2
; CHECK-NEXT: cmpu.l %s0, %s0, (58)1
-; CHECK-NEXT: cmov.l.lt %s2, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s3, %s2, %s1
-; CHECK-NEXT: brne.w 0, %s3, .LBB{{[0-9]+}}_2
+; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s0
+; CHECK-NEXT: cmpu.l %s0, %s1, (0)0
+; CHECK-NEXT: cmov.l.eq %s4, %s3, %s0
+; CHECK-NEXT: brne.w 0, %s4, .LBB{{[0-9]+}}_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: #APP
; CHECK-NEXT: nop
define signext i32 @brind(i32 signext %0) {
; CHECK-LABEL: brind:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 1, (0)1
-; CHECK-NEXT: cmps.w.sx %s1, %s0, %s1
+; CHECK-NEXT: cmpu.w %s1, %s0, (63)0
; CHECK-NEXT: lea %s2, .Ltmp0@lo
; CHECK-NEXT: and %s2, %s2, (32)0
; CHECK-NEXT: lea.sl %s2, .Ltmp0@hi(, %s2)
; CHECK-NEXT: and %s3, %s3, (32)0
; CHECK-NEXT: lea.sl %s3, .Ltmp1@hi(, %s3)
; CHECK-NEXT: cmov.w.eq %s2, %s3, %s1
-; CHECK-NEXT: or %s1, 0, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
; CHECK-NEXT: lea %s1, .Ltmp2@lo
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: lea.sl %s1, .Ltmp2@hi(, %s1)
define float @ull2f(i64 %x) {
; CHECK-LABEL: ull2f:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s2, %s0, (0)1
; CHECK-NEXT: cvt.d.l %s1, %s0
; CHECK-NEXT: cvt.s.d %s1, %s1
-; CHECK-NEXT: srl %s3, %s0, 1
-; CHECK-NEXT: and %s0, 1, %s0
-; CHECK-NEXT: or %s0, %s0, %s3
-; CHECK-NEXT: cvt.d.l %s0, %s0
-; CHECK-NEXT: cvt.s.d %s0, %s0
-; CHECK-NEXT: fadd.s %s0, %s0, %s0
-; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2
+; CHECK-NEXT: srl %s2, %s0, 1
+; CHECK-NEXT: and %s3, 1, %s0
+; CHECK-NEXT: or %s2, %s3, %s2
+; CHECK-NEXT: cvt.d.l %s2, %s2
+; CHECK-NEXT: cvt.s.d %s2, %s2
+; CHECK-NEXT: fadd.s %s2, %s2, %s2
+; CHECK-NEXT: cmov.l.lt %s1, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%r = uitofp i64 %x to float
define i128 @func128(i128 %p){
; CHECK-LABEL: func128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s2, %s1, (0)1
-; CHECK-NEXT: ldz %s1, %s1
+; CHECK-NEXT: ldz %s2, %s1
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, 64(, %s0)
-; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2
+; CHECK-NEXT: cmov.l.ne %s0, %s2, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 true)
define i128 @func128x(i128 %p){
; CHECK-LABEL: func128x:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s2, %s1, (0)1
-; CHECK-NEXT: ldz %s1, %s1
+; CHECK-NEXT: ldz %s2, %s1
; CHECK-NEXT: ldz %s0, %s0
; CHECK-NEXT: lea %s0, 64(, %s0)
-; CHECK-NEXT: cmov.l.ne %s0, %s1, %s2
+; CHECK-NEXT: cmov.l.ne %s0, %s2, %s1
; CHECK-NEXT: or %s1, 0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.ctlz.i128(i128 %p, i1 false)
define i128 @func128(i128 %p) {
; CHECK-LABEL: func128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s2, %s0, (0)1
-; CHECK-NEXT: lea %s3, -1(, %s0)
-; CHECK-NEXT: nnd %s0, %s0, %s3
-; CHECK-NEXT: pcnt %s3, %s0
-; CHECK-NEXT: lea %s0, -1(, %s1)
-; CHECK-NEXT: nnd %s0, %s1, %s0
-; CHECK-NEXT: pcnt %s0, %s0
-; CHECK-NEXT: lea %s0, 64(, %s0)
-; CHECK-NEXT: cmov.l.ne %s0, %s3, %s2
+; CHECK-NEXT: lea %s2, -1(, %s0)
+; CHECK-NEXT: nnd %s2, %s0, %s2
+; CHECK-NEXT: pcnt %s3, %s2
+; CHECK-NEXT: lea %s2, -1(, %s1)
+; CHECK-NEXT: nnd %s1, %s1, %s2
+; CHECK-NEXT: pcnt %s1, %s1
+; CHECK-NEXT: lea %s2, 64(, %s1)
+; CHECK-NEXT: cmov.l.ne %s2, %s3, %s0
; CHECK-NEXT: or %s1, 0, (0)1
+; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
%r = tail call i128 @llvm.cttz.i128(i128 %p, i1 true)
ret i128 %r
define float @ul2f(i64 %a) {
; CHECK-LABEL: ul2f:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: cmps.l %s2, %s0, (0)1
; CHECK-NEXT: cvt.d.l %s1, %s0
; CHECK-NEXT: cvt.s.d %s1, %s1
-; CHECK-NEXT: srl %s3, %s0, 1
-; CHECK-NEXT: and %s0, 1, %s0
-; CHECK-NEXT: or %s0, %s0, %s3
-; CHECK-NEXT: cvt.d.l %s0, %s0
-; CHECK-NEXT: cvt.s.d %s0, %s0
-; CHECK-NEXT: fadd.s %s0, %s0, %s0
-; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2
+; CHECK-NEXT: srl %s2, %s0, 1
+; CHECK-NEXT: and %s3, 1, %s0
+; CHECK-NEXT: or %s2, %s3, %s2
+; CHECK-NEXT: cvt.d.l %s2, %s2
+; CHECK-NEXT: cvt.s.d %s2, %s2
+; CHECK-NEXT: fadd.s %s2, %s2, %s2
+; CHECK-NEXT: cmov.l.lt %s1, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
entry:
define zeroext i1 @select_cc_i8_i1(i8 signext %0, i8 signext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_i8_i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i1 @select_cc_u8_i1(i8 zeroext %0, i8 zeroext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_u8_i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i1 @select_cc_i16_i1(i16 signext %0, i16 signext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_i16_i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i1 @select_cc_u16_i1(i16 zeroext %0, i16 zeroext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_u16_i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i1 @select_cc_i32_i1(i32 signext %0, i32 signext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_i32_i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i1 @select_cc_u32_i1(i32 zeroext %0, i32 zeroext %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_u32_i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i1 @select_cc_i64_i1(i64 %0, i64 %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_i64_i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i1 @select_cc_u64_i1(i64 %0, i64 %1, i1 zeroext %2, i1 zeroext %3) {
; CHECK-LABEL: select_cc_u64_i1:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i8 @select_cc_i8_i8(i8 signext %0, i8 signext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_i8_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i8 @select_cc_u8_i8(i8 zeroext %0, i8 zeroext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_u8_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i8 @select_cc_i16_i8(i16 signext %0, i16 signext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_i16_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i8 @select_cc_u16_i8(i16 zeroext %0, i16 zeroext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_u16_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i8 @select_cc_i32_i8(i32 signext %0, i32 signext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_i32_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i8 @select_cc_u32_i8(i32 zeroext %0, i32 zeroext %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_u32_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i8 @select_cc_i64_i8(i64 %0, i64 %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_i64_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i8 @select_cc_u64_i8(i64 %0, i64 %1, i8 signext %2, i8 signext %3) {
; CHECK-LABEL: select_cc_u64_i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i8 @select_cc_i8_u8(i8 signext %0, i8 signext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_i8_u8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i8 @select_cc_u8_u8(i8 zeroext %0, i8 zeroext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_u8_u8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i8 @select_cc_i16_u8(i16 signext %0, i16 signext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_i16_u8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i8 @select_cc_u16_u8(i16 zeroext %0, i16 zeroext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_u16_u8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i8 @select_cc_i32_u8(i32 signext %0, i32 signext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_i32_u8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i8 @select_cc_u32_u8(i32 zeroext %0, i32 zeroext %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_u32_u8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i8 @select_cc_i64_u8(i64 %0, i64 %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_i64_u8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i8 @select_cc_u64_u8(i64 %0, i64 %1, i8 zeroext %2, i8 zeroext %3) {
; CHECK-LABEL: select_cc_u64_u8:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i16 @select_cc_i8_i16(i8 signext %0, i8 signext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_i8_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i16 @select_cc_u8_i16(i8 zeroext %0, i8 zeroext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_u8_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i16 @select_cc_i16_i16(i16 signext %0, i16 signext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_i16_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i16 @select_cc_u16_i16(i16 zeroext %0, i16 zeroext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_u16_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i16 @select_cc_i32_i16(i32 signext %0, i32 signext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_i32_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i16 @select_cc_u32_i16(i32 zeroext %0, i32 zeroext %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_u32_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i16 @select_cc_i64_i16(i64 %0, i64 %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_i64_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i16 @select_cc_u64_i16(i64 %0, i64 %1, i16 signext %2, i16 signext %3) {
; CHECK-LABEL: select_cc_u64_i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i16 @select_cc_i8_u16(i8 signext %0, i8 signext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_i8_u16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i16 @select_cc_u8_u16(i8 zeroext %0, i8 zeroext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_u8_u16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i16 @select_cc_i16_u16(i16 signext %0, i16 signext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_i16_u16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i16 @select_cc_u16_u16(i16 zeroext %0, i16 zeroext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_u16_u16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i16 @select_cc_i32_u16(i32 signext %0, i32 signext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_i32_u16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i16 @select_cc_u32_u16(i32 zeroext %0, i32 zeroext %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_u32_u16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i16 @select_cc_i64_u16(i64 %0, i64 %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_i64_u16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i16 @select_cc_u64_u16(i64 %0, i64 %1, i16 zeroext %2, i16 zeroext %3) {
; CHECK-LABEL: select_cc_u64_u16:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i32 @select_cc_i8_i32(i8 signext %0, i8 signext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_i8_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i32 @select_cc_u8_i32(i8 zeroext %0, i8 zeroext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_u8_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i32 @select_cc_i16_i32(i16 signext %0, i16 signext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_i16_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i32 @select_cc_u16_i32(i16 zeroext %0, i16 zeroext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_u16_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i32 @select_cc_i32_i32(i32 signext %0, i32 signext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_i32_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i32 @select_cc_u32_i32(i32 zeroext %0, i32 zeroext %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_u32_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i32 @select_cc_i64_i32(i64 %0, i64 %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_i64_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define signext i32 @select_cc_u64_i32(i64 %0, i64 %1, i32 signext %2, i32 signext %3) {
; CHECK-LABEL: select_cc_u64_i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.sx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.sx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i32 @select_cc_i8_u32(i8 signext %0, i8 signext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_i8_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i32 @select_cc_u8_u32(i8 zeroext %0, i8 zeroext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_u8_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i32 @select_cc_i16_u32(i16 signext %0, i16 signext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_i16_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i32 @select_cc_u16_u32(i16 zeroext %0, i16 zeroext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_u16_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i32 @select_cc_i32_u32(i32 signext %0, i32 signext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_i32_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i32 @select_cc_u32_u32(i32 zeroext %0, i32 zeroext %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_u32_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i32 @select_cc_i64_u32(i64 %0, i64 %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_i64_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define zeroext i32 @select_cc_u64_u32(i64 %0, i64 %1, i32 zeroext %2, i32 zeroext %3) {
; CHECK-LABEL: select_cc_u64_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: adds.w.zx %s0, %s3, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: adds.w.zx %s0, %s5, (0)1
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_i8_i64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i8_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_u8_i64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u8_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_i16_i64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i16_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_u16_i64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u16_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_i32_i64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i32_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_u32_i64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u32_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_i64_i64(i64 %0, i64 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i64_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_u64_i64(i64 %0, i64 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u64_i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_i8_u64(i8 signext %0, i8 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i8_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_u8_u64(i8 zeroext %0, i8 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u8_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_i16_u64(i16 signext %0, i16 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i16_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_u16_u64(i16 zeroext %0, i16 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u16_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_i32_u64(i32 signext %0, i32 signext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i32_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_u32_u64(i32 zeroext %0, i32 zeroext %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u32_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_i64_u64(i64 %0, i64 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_i64_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @select_cc_u64_u64(i64 %0, i64 %1, i64 %2, i64 %3) {
; CHECK-LABEL: select_cc_u64_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
define i128 @select_cc_i8_i128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i8_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_u8_i128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u8_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_i16_i128(i16 signext %0, i16 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i16_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_u16_i128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u16_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_i32_i128(i32 signext %0, i32 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i32_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_u32_i128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u32_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_i64_i128(i64 %0, i64 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i64_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_u64_i128(i64 %0, i64 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u64_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6
define i128 @select_cc_i8_u128(i8 signext %0, i8 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i8_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_u8_u128(i8 zeroext %0, i8 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u8_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_i16_u128(i16 signext %0, i16 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i16_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_u16_u128(i16 zeroext %0, i16 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u16_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_i32_u128(i32 signext %0, i32 signext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i32_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_u32_u128(i32 zeroext %0, i32 zeroext %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u32_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_i64_u128(i64 %0, i64 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_i64_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define i128 @select_cc_u64_u128(i64 %0, i64 %1, i128 %2, i128 %3) {
; CHECK-LABEL: select_cc_u64_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6
define float @select_cc_i8_float(i8 signext %0, i8 signext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_i8_float:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @select_cc_u8_float(i8 zeroext %0, i8 zeroext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_u8_float:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @select_cc_i16_float(i16 signext %0, i16 signext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_i16_float:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @select_cc_u16_float(i16 zeroext %0, i16 zeroext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_u16_float:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @select_cc_i32_float(i32 signext %0, i32 signext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_i32_float:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @select_cc_u32_float(i32 zeroext %0, i32 zeroext %1, float %2, float %3) {
; CHECK-LABEL: select_cc_u32_float:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @select_cc_i64_float(i64 %0, i64 %1, float %2, float %3) {
; CHECK-LABEL: select_cc_i64_float:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @select_cc_u64_float(i64 %0, i64 %1, float %2, float %3) {
; CHECK-LABEL: select_cc_u64_float:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
define double @select_cc_i8_double(i8 signext %0, i8 signext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_i8_double:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @select_cc_u8_double(i8 zeroext %0, i8 zeroext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_u8_double:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @select_cc_i16_double(i16 signext %0, i16 signext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_i16_double:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @select_cc_u16_double(i16 zeroext %0, i16 zeroext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_u16_double:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @select_cc_i32_double(i32 signext %0, i32 signext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_i32_double:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @select_cc_u32_double(i32 zeroext %0, i32 zeroext %1, double %2, double %3) {
; CHECK-LABEL: select_cc_u32_double:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @select_cc_i64_double(i64 %0, i64 %1, double %2, double %3) {
; CHECK-LABEL: select_cc_i64_double:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @select_cc_u64_double(i64 %0, i64 %1, double %2, double %3) {
; CHECK-LABEL: select_cc_u64_double:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s5, %s4, %s0
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
define fp128 @select_cc_i8_quad(i8 signext %0, i8 signext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_i8_quad:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define fp128 @select_cc_u8_quad(i8 zeroext %0, i8 zeroext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_u8_quad:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define fp128 @select_cc_i16_quad(i16 signext %0, i16 signext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_i16_quad:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define fp128 @select_cc_u16_quad(i16 zeroext %0, i16 zeroext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_u16_quad:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define fp128 @select_cc_i32_quad(i32 signext %0, i32 signext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_i32_quad:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define fp128 @select_cc_u32_quad(i32 zeroext %0, i32 zeroext %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_u32_quad:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.w.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define fp128 @select_cc_i64_quad(i64 %0, i64 %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_i64_quad:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
define fp128 @select_cc_u64_quad(i64 %0, i64 %1, fp128 %2, fp128 %3) {
; CHECK-LABEL: select_cc_u64_quad:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: cmov.l.eq %s5, %s3, %s0
; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: xor %s1, %s1, %s3
; CHECK-NEXT: xor %s0, %s0, %s2
; CHECK-NEXT: or %s0, %s0, %s1
-; CHECK-NEXT: cmps.l %s0, %s0, (0)1
; CHECK-NEXT: cmov.l.eq %s6, %s4, %s0
; CHECK-NEXT: cmov.l.eq %s7, %s5, %s0
; CHECK-NEXT: or %s0, 0, %s6
; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccsgti32(i32, i32, float, float) {
; CHECK-LABEL: selectccsgti32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccsgti128(i128, i128, float, float) {
; CHECK-LABEL: selectccsgti128:
; CHECK: # %bb.0:
+; CHECK-NEXT: cmpu.l %s6, %s1, %s3
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1
-; CHECK-NEXT: or %s6, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1
+; CHECK-NEXT: or %s7, 0, (0)1
+; CHECK-NEXT: cmov.l.gt %s7, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
-; CHECK-NEXT: or %s2, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1
-; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
-; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
+; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s7, %s3, %s6
+; CHECK-NEXT: cmov.w.ne %s5, %s4, %s7
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1
define float @selectccoeq(float, float, float, float) {
; CHECK-LABEL: selectccoeq:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccone(float, float, float, float) {
; CHECK-LABEL: selectccone:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccogt(float, float, float, float) {
; CHECK-LABEL: selectccogt:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccoge(float, float, float, float) {
; CHECK-LABEL: selectccoge:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccolt(float, float, float, float) {
; CHECK-LABEL: selectccolt:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccole(float, float, float, float) {
; CHECK-LABEL: selectccole:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccueq(float, float, float, float) {
; CHECK-LABEL: selectccueq:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.eqnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccune(float, float, float, float) {
; CHECK-LABEL: selectccune:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.nenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccugt(float, float, float, float) {
; CHECK-LABEL: selectccugt:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.gtnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccuge(float, float, float, float) {
; CHECK-LABEL: selectccuge:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.genan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccult(float, float, float, float) {
; CHECK-LABEL: selectccult:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.ltnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define float @selectccule(float, float, float, float) {
; CHECK-LABEL: selectccule:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.s %s0, %s0, %s1
; CHECK-NEXT: cmov.s.lenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccsgti32(i32, i32, double, double) {
; CHECK-LABEL: selectccsgti32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccsgti128(i128, i128, double, double) {
; CHECK-LABEL: selectccsgti128:
; CHECK: # %bb.0:
+; CHECK-NEXT: cmpu.l %s6, %s1, %s3
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1
-; CHECK-NEXT: or %s6, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1
+; CHECK-NEXT: or %s7, 0, (0)1
+; CHECK-NEXT: cmov.l.gt %s7, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
-; CHECK-NEXT: or %s2, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1
-; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
-; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
+; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s7, %s3, %s6
+; CHECK-NEXT: cmov.w.ne %s5, %s4, %s7
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1
define double @selectccoeq(double, double, double, double) {
; CHECK-LABEL: selectccoeq:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccone(double, double, double, double) {
; CHECK-LABEL: selectccone:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccogt(double, double, double, double) {
; CHECK-LABEL: selectccogt:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccoge(double, double, double, double) {
; CHECK-LABEL: selectccoge:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccolt(double, double, double, double) {
; CHECK-LABEL: selectccolt:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccole(double, double, double, double) {
; CHECK-LABEL: selectccole:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccueq(double, double, double, double) {
; CHECK-LABEL: selectccueq:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.eqnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccune(double, double, double, double) {
; CHECK-LABEL: selectccune:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.nenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccugt(double, double, double, double) {
; CHECK-LABEL: selectccugt:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.gtnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccuge(double, double, double, double) {
; CHECK-LABEL: selectccuge:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.genan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccult(double, double, double, double) {
; CHECK-LABEL: selectccult:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.ltnan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define double @selectccule(double, double, double, double) {
; CHECK-LABEL: selectccule:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea.sl %s1, 0
-; CHECK-NEXT: fcmp.d %s0, %s0, %s1
; CHECK-NEXT: cmov.d.lenan %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i32 @selectcceq(i32, i32, i32, i32) {
; CHECK-LABEL: selectcceq:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i32 @selectccne(i32, i32, i32, i32) {
; CHECK-LABEL: selectccne:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i32 @selectccsgt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgt:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i32 @selectccsge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsge:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.ge %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i32 @selectccslt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccslt:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i32 @selectccsle(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsle:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.le %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i32 @selectccsgti32(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgti32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i32 @selectccsgti128(i128, i128, i32, i32) {
; CHECK-LABEL: selectccsgti128:
; CHECK: # %bb.0:
+; CHECK-NEXT: cmpu.l %s6, %s1, %s3
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1
-; CHECK-NEXT: or %s6, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1
+; CHECK-NEXT: or %s7, 0, (0)1
+; CHECK-NEXT: cmov.l.gt %s7, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
-; CHECK-NEXT: or %s2, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1
-; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
-; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
+; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s7, %s3, %s6
+; CHECK-NEXT: cmov.w.ne %s5, %s4, %s7
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1
define i32 @selectcceq(i32, i32, i32, i32) {
; CHECK-LABEL: selectcceq:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, 12, %s0
; CHECK-NEXT: cmov.w.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i32 @selectccne(i32, i32, i32, i32) {
; CHECK-LABEL: selectccne:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmpu.w %s0, 12, %s0
; CHECK-NEXT: cmov.w.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i32 @selectccsgt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsgt:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: cmps.w.zx %s0, 12, %s0
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i32 %0, 12
define i32 @selectccsge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsge:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: cmps.w.zx %s0, 11, %s0
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sge i32 %0, 12
define i32 @selectccslt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccslt:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: cmps.w.zx %s0, 12, %s0
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp slt i32 %0, 12
define i32 @selectccsle(i32, i32, i32, i32) {
; CHECK-LABEL: selectccsle:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: cmps.w.zx %s0, 13, %s0
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sle i32 %0, 12
define i32 @selectccugt(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.w %s0, 12, %s0
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i32 %0, 12
define i32 @selectccuge(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.w %s0, 11, %s0
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i32 %0, 12
define i32 @selectccult(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.w %s0, 12, %s0
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i32 %0, 12
define i32 @selectccule(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.w %s0, 13, %s0
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i32 %0, 12
define i32 @selectccugt2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccugt2:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.w %s0, 12, %s0
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i32 %0, 12
define i32 @selectccuge2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccuge2:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.w %s0, 11, %s0
+; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i32 %0, 12
define i32 @selectccult2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccult2:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.w %s0, 12, %s0
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i32 %0, 12
define i32 @selectccule2(i32, i32, i32, i32) {
; CHECK-LABEL: selectccule2:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmpu.w %s0, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.w %s0, 13, %s0
+; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i32 %0, 12
define i64 @selectcceq(i64, i64, i64, i64) {
; CHECK-LABEL: selectcceq:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @selectccne(i64, i64, i64, i64) {
; CHECK-LABEL: selectccne:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, %s0, %s1
; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: sra.l %s1, %s1, 56
; CHECK-NEXT: sll %s0, %s0, 56
; CHECK-NEXT: sra.l %s0, %s0, 56
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: sra.l %s1, %s1, 48
; CHECK-NEXT: sll %s0, %s0, 48
; CHECK-NEXT: sra.l %s0, %s0, 48
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @selectccsgti32(i32, i32, i64, i64) {
; CHECK-LABEL: selectccsgti32:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.w.sx %s0, %s0, %s1
+; CHECK-NEXT: cmps.w.zx %s0, %s0, %s1
; CHECK-NEXT: cmov.w.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @selectccsgti128(i128, i128, i64, i64) {
; CHECK-LABEL: selectccsgti128:
; CHECK: # %bb.0:
+; CHECK-NEXT: cmpu.l %s6, %s1, %s3
; CHECK-NEXT: cmps.l %s1, %s1, %s3
; CHECK-NEXT: or %s3, 0, (0)1
-; CHECK-NEXT: or %s6, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s6, (63)0, %s1
+; CHECK-NEXT: or %s7, 0, (0)1
+; CHECK-NEXT: cmov.l.gt %s7, (63)0, %s1
; CHECK-NEXT: cmpu.l %s0, %s0, %s2
-; CHECK-NEXT: or %s2, 0, (0)1
-; CHECK-NEXT: cmov.l.gt %s2, (63)0, %s0
-; CHECK-NEXT: cmov.l.eq %s6, %s2, %s1
-; CHECK-NEXT: cmps.w.sx %s0, %s6, %s3
-; CHECK-NEXT: cmov.w.ne %s5, %s4, %s0
+; CHECK-NEXT: cmov.l.gt %s3, (63)0, %s0
+; CHECK-NEXT: cmov.l.eq %s7, %s3, %s6
+; CHECK-NEXT: cmov.w.ne %s5, %s4, %s7
; CHECK-NEXT: or %s0, 0, %s5
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i128 %0, %1
define i64 @selectcceq(i64, i64, i64, i64) {
; CHECK-LABEL: selectcceq:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, 12, %s0
; CHECK-NEXT: cmov.l.eq %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @selectccne(i64, i64, i64, i64) {
; CHECK-LABEL: selectccne:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
+; CHECK-NEXT: cmpu.l %s0, 12, %s0
; CHECK-NEXT: cmov.l.ne %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
define i64 @selectccsgt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsgt:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
+; CHECK-NEXT: cmps.l %s0, 12, %s0
+; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sgt i64 %0, 12
define i64 @selectccsge(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsge:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
+; CHECK-NEXT: cmps.l %s0, 11, %s0
+; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sge i64 %0, 12
define i64 @selectccslt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccslt:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
+; CHECK-NEXT: cmps.l %s0, 12, %s0
+; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp slt i64 %0, 12
define i64 @selectccsle(i64, i64, i64, i64) {
; CHECK-LABEL: selectccsle:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmps.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
+; CHECK-NEXT: cmps.l %s0, 13, %s0
+; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp sle i64 %0, 12
define i64 @selectccugt(i64, i64, i64, i64) {
; CHECK-LABEL: selectccugt:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.l %s0, 12, %s0
+; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i64 %0, 12
define i64 @selectccuge(i64, i64, i64, i64) {
; CHECK-LABEL: selectccuge:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmpu.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.l %s0, 11, %s0
+; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i64 %0, 12
define i64 @selectccult(i64, i64, i64, i64) {
; CHECK-LABEL: selectccult:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.l %s0, 12, %s0
+; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i64 %0, 12
define i64 @selectccule(i64, i64, i64, i64) {
; CHECK-LABEL: selectccule:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmpu.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.l %s0, 13, %s0
+; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i64 %0, 12
define i64 @selectccugt2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccugt2:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.l %s0, 12, %s0
+; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ugt i64 %0, 12
define i64 @selectccuge2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccuge2:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 11, (0)1
-; CHECK-NEXT: cmpu.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.l %s0, 11, %s0
+; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp uge i64 %0, 12
define i64 @selectccult2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccult2:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 12, (0)1
-; CHECK-NEXT: cmpu.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.l %s0, 12, %s0
+; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ult i64 %0, 12
define i64 @selectccule2(i64, i64, i64, i64) {
; CHECK-LABEL: selectccule2:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s1, 13, (0)1
-; CHECK-NEXT: cmpu.l %s0, %s0, %s1
-; CHECK-NEXT: cmov.l.lt %s3, %s2, %s0
+; CHECK-NEXT: cmpu.l %s0, 13, %s0
+; CHECK-NEXT: cmov.l.gt %s3, %s2, %s0
; CHECK-NEXT: or %s0, 0, %s3
; CHECK-NEXT: b.l.t (, %s10)
%5 = icmp ule i64 %0, 12
; CHECK-NEXT: cmps.l %s5, %s1, %s3
; CHECK-NEXT: or %s4, 0, %s2
; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5
-; CHECK-NEXT: cmpu.l %s6, %s0, %s2
-; CHECK-NEXT: cmov.l.gt %s2, %s0, %s6
-; CHECK-NEXT: cmov.l.eq %s4, %s2, %s5
+; CHECK-NEXT: cmpu.l %s5, %s0, %s2
+; CHECK-NEXT: cmov.l.gt %s2, %s0, %s5
+; CHECK-NEXT: cmpu.l %s0, %s1, %s3
+; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: maxs.l %s1, %s1, %s3
; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: b.l.t (, %s10)
define i128 @func_smax_fore_zero_i128(i128 noundef %0) {
; CHECK-LABEL: func_smax_fore_zero_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s2, 0, (0)1
-; CHECK-NEXT: cmps.l %s3, %s1, (0)1
-; CHECK-NEXT: cmov.l.gt %s2, %s0, %s3
-; CHECK-NEXT: cmov.l.eq %s2, %s0, %s3
+; CHECK-NEXT: or %s2, 0, %s0
+; CHECK-NEXT: cmov.l.le %s2, (0)1, %s1
+; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1
; CHECK-NEXT: maxs.l %s1, 0, %s1
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
define i128 @func_smax_back_zero_i128(i128 noundef %0) {
; CHECK-LABEL: func_smax_back_zero_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s2, 0, (0)1
-; CHECK-NEXT: cmps.l %s3, %s1, (0)1
-; CHECK-NEXT: cmov.l.gt %s2, %s0, %s3
-; CHECK-NEXT: cmov.l.eq %s2, %s0, %s3
+; CHECK-NEXT: or %s2, 0, %s0
+; CHECK-NEXT: cmov.l.le %s2, (0)1, %s1
+; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1
; CHECK-NEXT: maxs.l %s1, 0, %s1
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
define i128 @func_smax_fore_const_i128(i128 noundef %0) {
; CHECK-LABEL: func_smax_fore_const_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s3, %s1, (0)1
-; CHECK-NEXT: lea %s4, 255
-; CHECK-NEXT: lea %s2, 255
-; CHECK-NEXT: cmov.l.gt %s2, %s0, %s3
-; CHECK-NEXT: cmpu.l %s5, %s0, (56)0
-; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5
-; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3
+; CHECK-NEXT: or %s2, 0, %s0
+; CHECK-NEXT: cmov.l.le %s2, (56)0, %s1
+; CHECK-NEXT: cmpu.l %s3, %s0, (56)0
+; CHECK-NEXT: cmov.l.le %s0, (56)0, %s3
+; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1
; CHECK-NEXT: maxs.l %s1, 0, %s1
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
define i128 @func_smax_back_const_i128(i128 noundef %0) {
; CHECK-LABEL: func_smax_back_const_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s3, %s1, (0)1
-; CHECK-NEXT: lea %s4, 255
-; CHECK-NEXT: lea %s2, 255
-; CHECK-NEXT: cmov.l.gt %s2, %s0, %s3
-; CHECK-NEXT: cmpu.l %s5, %s0, (56)0
-; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5
-; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3
+; CHECK-NEXT: or %s2, 0, %s0
+; CHECK-NEXT: cmov.l.le %s2, (56)0, %s1
+; CHECK-NEXT: cmpu.l %s3, %s0, (56)0
+; CHECK-NEXT: cmov.l.le %s0, (56)0, %s3
+; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1
; CHECK-NEXT: maxs.l %s1, 0, %s1
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: cmps.l %s5, %s1, %s3
; CHECK-NEXT: or %s4, 0, %s2
; CHECK-NEXT: cmov.l.lt %s4, %s0, %s5
-; CHECK-NEXT: cmpu.l %s6, %s0, %s2
-; CHECK-NEXT: cmov.l.lt %s2, %s0, %s6
-; CHECK-NEXT: cmov.l.eq %s4, %s2, %s5
+; CHECK-NEXT: cmpu.l %s5, %s0, %s2
+; CHECK-NEXT: cmov.l.lt %s2, %s0, %s5
+; CHECK-NEXT: cmpu.l %s0, %s1, %s3
+; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
; CHECK-NEXT: mins.l %s1, %s1, %s3
; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: b.l.t (, %s10)
define i128 @func_smin_fore_zero_i128(i128 noundef %0) {
; CHECK-LABEL: func_smin_fore_zero_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s2, 0, (0)1
-; CHECK-NEXT: cmps.l %s3, %s1, (0)1
-; CHECK-NEXT: sra.l %s4, %s1, 63
-; CHECK-NEXT: and %s0, %s4, %s0
-; CHECK-NEXT: cmov.l.eq %s0, %s2, %s3
+; CHECK-NEXT: sra.l %s2, %s1, 63
+; CHECK-NEXT: and %s0, %s2, %s0
+; CHECK-NEXT: cmov.l.eq %s0, (0)1, %s1
; CHECK-NEXT: mins.l %s1, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i128 @llvm.smin.i128(i128 %0, i128 0)
define i128 @func_smin_back_zero_i128(i128 noundef %0) {
; CHECK-LABEL: func_smin_back_zero_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: or %s2, 0, (0)1
-; CHECK-NEXT: cmps.l %s3, %s1, (0)1
-; CHECK-NEXT: sra.l %s4, %s1, 63
-; CHECK-NEXT: and %s0, %s4, %s0
-; CHECK-NEXT: cmov.l.eq %s0, %s2, %s3
+; CHECK-NEXT: sra.l %s2, %s1, 63
+; CHECK-NEXT: and %s0, %s2, %s0
+; CHECK-NEXT: cmov.l.eq %s0, (0)1, %s1
; CHECK-NEXT: mins.l %s1, 0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i128 @llvm.smin.i128(i128 %0, i128 0)
define i128 @func_smin_fore_const_i128(i128 noundef %0) {
; CHECK-LABEL: func_smin_fore_const_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s3, %s1, (0)1
-; CHECK-NEXT: lea %s4, 255
-; CHECK-NEXT: lea %s2, 255
-; CHECK-NEXT: cmov.l.lt %s2, %s0, %s3
-; CHECK-NEXT: cmpu.l %s5, %s0, (56)0
-; CHECK-NEXT: cmov.l.lt %s4, %s0, %s5
-; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3
+; CHECK-NEXT: or %s2, 0, %s0
+; CHECK-NEXT: cmov.l.ge %s2, (56)0, %s1
+; CHECK-NEXT: cmpu.l %s3, %s0, (56)0
+; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s3
+; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1
; CHECK-NEXT: mins.l %s1, 0, %s1
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
define i128 @func_smin_back_const_i128(i128 noundef %0) {
; CHECK-LABEL: func_smin_back_const_i128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s3, %s1, (0)1
-; CHECK-NEXT: lea %s4, 255
-; CHECK-NEXT: lea %s2, 255
-; CHECK-NEXT: cmov.l.lt %s2, %s0, %s3
-; CHECK-NEXT: cmpu.l %s5, %s0, (56)0
-; CHECK-NEXT: cmov.l.lt %s4, %s0, %s5
-; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3
+; CHECK-NEXT: or %s2, 0, %s0
+; CHECK-NEXT: cmov.l.ge %s2, (56)0, %s1
+; CHECK-NEXT: cmpu.l %s3, %s0, (56)0
+; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s3
+; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1
; CHECK-NEXT: mins.l %s1, 0, %s1
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5
; CHECK-NEXT: cmpu.l %s6, %s0, %s2
; CHECK-NEXT: cmov.l.gt %s2, %s0, %s6
-; CHECK-NEXT: cmps.l %s0, %s1, %s3
-; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
+; CHECK-NEXT: cmov.l.eq %s4, %s2, %s5
; CHECK-NEXT: cmov.l.gt %s3, %s1, %s5
; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s3
define zeroext i32 @func_umax_fore_const_u32(i32 noundef zeroext %0) {
; CHECK-LABEL: func_umax_fore_const_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s1, 255
-; CHECK-NEXT: cmpu.w %s2, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2
-; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s0, (56)0
+; CHECK-NEXT: cmov.w.le %s0, (56)0, %s1
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i32 @llvm.umax.i32(i32 %0, i32 255)
ret i32 %2
define i64 @func_umax_fore_const_u64(i64 noundef %0) {
; CHECK-LABEL: func_umax_fore_const_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s1, 255
-; CHECK-NEXT: cmpu.l %s2, %s0, (56)0
-; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2
-; CHECK-NEXT: or %s0, 0, %s1
+; CHECK-NEXT: cmpu.l %s1, %s0, (56)0
+; CHECK-NEXT: cmov.l.le %s0, (56)0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i64 @llvm.umax.i64(i64 %0, i64 255)
ret i64 %2
define i128 @func_umax_fore_const_u128(i128 noundef %0) {
; CHECK-LABEL: func_umax_fore_const_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s3, %s1, (0)1
-; CHECK-NEXT: lea %s4, 255
-; CHECK-NEXT: lea %s2, 255
-; CHECK-NEXT: cmov.l.ne %s2, %s0, %s3
-; CHECK-NEXT: cmpu.l %s5, %s0, (56)0
-; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5
-; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3
+; CHECK-NEXT: or %s2, 0, %s0
+; CHECK-NEXT: cmov.l.eq %s2, (56)0, %s1
+; CHECK-NEXT: cmpu.l %s3, %s0, (56)0
+; CHECK-NEXT: cmov.l.le %s0, (56)0, %s3
+; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i128 @llvm.umax.i128(i128 %0, i128 255)
define zeroext i32 @func_umax_back_const_u32(i32 noundef zeroext %0) {
; CHECK-LABEL: func_umax_back_const_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s1, 255
-; CHECK-NEXT: cmpu.w %s2, %s0, %s1
-; CHECK-NEXT: cmov.w.gt %s1, %s0, %s2
-; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s0, (56)0
+; CHECK-NEXT: cmov.w.le %s0, (56)0, %s1
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i32 @llvm.umax.i32(i32 %0, i32 255)
ret i32 %2
define i64 @func_umax_back_const_u64(i64 noundef %0) {
; CHECK-LABEL: func_umax_back_const_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s1, 255
-; CHECK-NEXT: cmpu.l %s2, %s0, (56)0
-; CHECK-NEXT: cmov.l.gt %s1, %s0, %s2
-; CHECK-NEXT: or %s0, 0, %s1
+; CHECK-NEXT: cmpu.l %s1, %s0, (56)0
+; CHECK-NEXT: cmov.l.le %s0, (56)0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i64 @llvm.umax.i64(i64 %0, i64 255)
ret i64 %2
define i128 @func_umax_back_const_u128(i128 noundef %0) {
; CHECK-LABEL: func_umax_back_const_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: cmps.l %s3, %s1, (0)1
-; CHECK-NEXT: lea %s4, 255
-; CHECK-NEXT: lea %s2, 255
-; CHECK-NEXT: cmov.l.ne %s2, %s0, %s3
-; CHECK-NEXT: cmpu.l %s5, %s0, (56)0
-; CHECK-NEXT: cmov.l.gt %s4, %s0, %s5
-; CHECK-NEXT: cmov.l.eq %s2, %s4, %s3
+; CHECK-NEXT: or %s2, 0, %s0
+; CHECK-NEXT: cmov.l.eq %s2, (56)0, %s1
+; CHECK-NEXT: cmpu.l %s3, %s0, (56)0
+; CHECK-NEXT: cmov.l.le %s0, (56)0, %s3
+; CHECK-NEXT: cmov.l.eq %s2, %s0, %s1
; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i128 @llvm.umax.i128(i128 %0, i128 255)
; CHECK-NEXT: cmov.l.lt %s4, %s0, %s5
; CHECK-NEXT: cmpu.l %s6, %s0, %s2
; CHECK-NEXT: cmov.l.lt %s2, %s0, %s6
-; CHECK-NEXT: cmps.l %s0, %s1, %s3
-; CHECK-NEXT: cmov.l.eq %s4, %s2, %s0
+; CHECK-NEXT: cmov.l.eq %s4, %s2, %s5
; CHECK-NEXT: cmov.l.lt %s3, %s1, %s5
; CHECK-NEXT: or %s0, 0, %s4
; CHECK-NEXT: or %s1, 0, %s3
define zeroext i32 @func_umin_fore_const_u32(i32 noundef zeroext %0) {
; CHECK-LABEL: func_umin_fore_const_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s1, 255
-; CHECK-NEXT: cmpu.w %s2, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2
-; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s0, (56)0
+; CHECK-NEXT: cmov.w.ge %s0, (56)0, %s1
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i32 @llvm.umin.i32(i32 %0, i32 255)
ret i32 %2
define i64 @func_umin_fore_const_u64(i64 noundef %0) {
; CHECK-LABEL: func_umin_fore_const_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s1, 255
-; CHECK-NEXT: cmpu.l %s2, %s0, (56)0
-; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2
-; CHECK-NEXT: or %s0, 0, %s1
+; CHECK-NEXT: cmpu.l %s1, %s0, (56)0
+; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i64 @llvm.umin.i64(i64 %0, i64 255)
ret i64 %2
define i128 @func_umin_fore_const_u128(i128 noundef %0) {
; CHECK-LABEL: func_umin_fore_const_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s2, 255
-; CHECK-NEXT: cmpu.l %s3, %s0, (56)0
-; CHECK-NEXT: lea %s4, 255
-; CHECK-NEXT: cmov.l.lt %s4, %s0, %s3
-; CHECK-NEXT: cmps.l %s0, %s1, (0)1
-; CHECK-NEXT: cmov.l.eq %s2, %s4, %s0
+; CHECK-NEXT: cmpu.l %s2, %s0, (56)0
+; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s2
+; CHECK-NEXT: cmov.l.ne %s0, (56)0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
-; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i128 @llvm.umin.i128(i128 %0, i128 255)
ret i128 %2
define zeroext i32 @func_umin_back_const_u32(i32 noundef zeroext %0) {
; CHECK-LABEL: func_umin_back_const_u32:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s1, 255
-; CHECK-NEXT: cmpu.w %s2, %s0, %s1
-; CHECK-NEXT: cmov.w.lt %s1, %s0, %s2
-; CHECK-NEXT: adds.w.zx %s0, %s1, (0)1
+; CHECK-NEXT: cmpu.w %s1, %s0, (56)0
+; CHECK-NEXT: cmov.w.ge %s0, (56)0, %s1
+; CHECK-NEXT: adds.w.zx %s0, %s0, (0)1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i32 @llvm.umin.i32(i32 %0, i32 255)
ret i32 %2
define i64 @func_umin_back_const_u64(i64 noundef %0) {
; CHECK-LABEL: func_umin_back_const_u64:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s1, 255
-; CHECK-NEXT: cmpu.l %s2, %s0, (56)0
-; CHECK-NEXT: cmov.l.lt %s1, %s0, %s2
-; CHECK-NEXT: or %s0, 0, %s1
+; CHECK-NEXT: cmpu.l %s1, %s0, (56)0
+; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s1
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i64 @llvm.umin.i64(i64 %0, i64 255)
ret i64 %2
define i128 @func_umin_back_const_u128(i128 noundef %0) {
; CHECK-LABEL: func_umin_back_const_u128:
; CHECK: # %bb.0:
-; CHECK-NEXT: lea %s2, 255
-; CHECK-NEXT: cmpu.l %s3, %s0, (56)0
-; CHECK-NEXT: lea %s4, 255
-; CHECK-NEXT: cmov.l.lt %s4, %s0, %s3
-; CHECK-NEXT: cmps.l %s0, %s1, (0)1
-; CHECK-NEXT: cmov.l.eq %s2, %s4, %s0
+; CHECK-NEXT: cmpu.l %s2, %s0, (56)0
+; CHECK-NEXT: cmov.l.ge %s0, (56)0, %s2
+; CHECK-NEXT: cmov.l.ne %s0, (56)0, %s1
; CHECK-NEXT: or %s1, 0, (0)1
-; CHECK-NEXT: or %s0, 0, %s2
; CHECK-NEXT: b.l.t (, %s10)
%2 = tail call i128 @llvm.umin.i128(i128 %0, i128 255)
ret i128 %2