cl_mem_unmap_auto((cl_mem)image);
}
-static const uint32_t tile_sz = 4096; /* 4KB per tile */
-static const uint32_t tilex_w = 512; /* tileX width in bytes */
-static const uint32_t tilex_h = 8; /* tileX height in number of rows */
-static const uint32_t tiley_w = 128; /* tileY width in bytes */
-static const uint32_t tiley_h = 32; /* tileY height in number of rows */
-static const uint32_t valign = 2; /* vertical alignment is 2. */
-
cl_image_tiling_t cl_get_default_tiling(void)
{
static int initialized = 0;
/* Tiling requires to align both pitch and height */
if (tiling == CL_NO_TILE) {
aligned_pitch = w * bpp;
- aligned_h = ALIGN(h, valign);
+ aligned_h = ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_NO_TILE, 1));
} else if (tiling == CL_TILE_X) {
- aligned_pitch = ALIGN(w * bpp, tilex_w);
- aligned_h = ALIGN(h, tilex_h);
+ aligned_pitch = ALIGN(w * bpp, cl_buffer_get_tiling_align(ctx, CL_TILE_X, 0));
+ aligned_h = ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_TILE_X, 1));
} else if (tiling == CL_TILE_Y) {
- aligned_pitch = ALIGN(w * bpp, tiley_w);
- aligned_h = ALIGN(h, tiley_h);
+ aligned_pitch = ALIGN(w * bpp, cl_buffer_get_tiling_align(ctx, CL_TILE_Y, 0));
+ aligned_h = ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_TILE_Y, 1));
}
sz = aligned_pitch * aligned_h * depth;
image_type == CL_MEM_OBJECT_IMAGE1D_BUFFER)
aligned_slice_pitch = 0;
else
- aligned_slice_pitch = aligned_pitch * ALIGN(h, 2);
+ aligned_slice_pitch = aligned_pitch * ALIGN(h, cl_buffer_get_tiling_align(ctx, CL_NO_TILE, 1));
cl_mem_image_init(cl_mem_image(mem), w, h, image_type, depth, *fmt,
intel_fmt, bpp, aligned_pitch, aligned_slice_pitch, tiling,
return CL_NO_TILE;
}
+static uint32_t intel_buffer_get_tiling_align(cl_context ctx, uint32_t tiling_mode, uint32_t dim)
+{
+ uint32_t gen_ver = ((intel_driver_t *)ctx->drv)->gen_ver;
+ uint32_t ret = 0;
+
+ switch (tiling_mode) {
+ case CL_TILE_X:
+ if (dim == 0) { //tileX width in bytes
+ ret = 512;
+ } else if (dim == 1) { //tileX height in number of rows
+ ret = 8;
+ } else
+ assert(0);
+ break;
+
+ case CL_TILE_Y:
+ if (dim == 0) { //tileY width in bytes
+ ret = 128;
+ } else if (dim == 1) { //tileY height in number of rows
+ ret = 32;
+ } else
+ assert(0);
+ break;
+
+ case CL_NO_TILE:
+ if (dim == 1) { //vertical alignment
+ if (gen_ver == 8)
+ ret = 4;
+ else
+ ret = 2;
+ } else
+ assert(0);
+ break;
+ }
+
+ return ret;
+}
+
#if defined(HAS_EGL)
#include "intel_dri_resource_sharing.h"
#include "cl_image.h"
cl_buffer_subdata = (cl_buffer_subdata_cb *) drm_intel_bo_subdata;
cl_buffer_wait_rendering = (cl_buffer_wait_rendering_cb *) drm_intel_bo_wait_rendering;
cl_buffer_get_fd = (cl_buffer_get_fd_cb *) drm_intel_bo_gem_export_to_prime;
+ cl_buffer_get_tiling_align = (cl_buffer_get_tiling_align_cb *)intel_buffer_get_tiling_align;
intel_set_gpgpu_callbacks(intel_get_device_id());
}
ss->ss0.surface_format = format;
if (intel_is_surface_array(type)) {
ss->ss0.surface_array = 1;
+ ss->ss1.surface_qpitch = (h + 3)/4;
}
ss->ss0.horizontal_alignment = 1;
ss->ss0.vertical_alignment = 1;
ss->ss3.surface_pitch = pitch - 1;
ss->ss1.mem_obj_ctrl_state = cl_gpgpu_get_cache_ctrl();
- ss->ss7.red_clear_color = 1;
ss->ss7.shader_channel_select_red = I965_SURCHAN_SELECT_RED;
ss->ss7.shader_channel_select_green = I965_SURCHAN_SELECT_GREEN;
ss->ss7.shader_channel_select_blue = I965_SURCHAN_SELECT_BLUE;