CHECK___builtin_cpu_is ("sierraforest");
cpu_model->__cpu_type = INTEL_SIERRAFOREST;
break;
+ case 0xad:
+ case 0xae:
+ /* Granite Rapids. */
+ cpu = "graniterapids";
+ CHECK___builtin_cpu_is ("corei7");
+ CHECK___builtin_cpu_is ("graniterapids");
+ cpu_model->__cpu_type = INTEL_COREI7;
+ cpu_model->__cpu_subtype = INTEL_COREI7_GRANITERAPIDS;
+ break;
case 0x17:
case 0x1d:
/* Penryn. */
"sapphirerapids",
"alderlake",
"rocketlake",
+ "graniterapids",
"intel",
"lujiazui",
"geode",
M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
{"meteorlake", PROCESSOR_ALDERLAKE, CPU_HASWELL, PTA_ALDERLAKE,
M_CPU_SUBTYPE (INTEL_COREI7_ALDERLAKE), P_PROC_AVX2},
+ {"graniterapids", PROCESSOR_GRANITERAPIDS, CPU_HASWELL, PTA_GRANITERAPIDS,
+ M_CPU_SUBTYPE (INTEL_COREI7_GRANITERAPIDS), P_PROC_AVX512F},
{"bonnell", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
M_CPU_TYPE (INTEL_BONNELL), P_PROC_SSSE3},
{"atom", PROCESSOR_BONNELL, CPU_ATOM, PTA_BONNELL,
INTEL_COREI7_ROCKETLAKE,
ZHAOXIN_FAM7H_LUJIAZUI,
AMDFAM19H_ZNVER4,
+ INTEL_COREI7_GRANITERAPIDS,
CPU_SUBTYPE_MAX
};
skylake goldmont goldmont-plus tremont cascadelake tigerlake cooperlake \
sapphirerapids alderlake rocketlake eden-x2 nano nano-1000 nano-2000 nano-3000 \
nano-x2 eden-x4 nano-x4 lujiazui x86-64 x86-64-v2 x86-64-v3 x86-64-v4 \
-sierraforest native"
+sierraforest graniterapids native"
# Additional x86 processors supported by --with-cpu=. Each processor
# MUST be separated by exactly one space.
/* This is unknown family 0x6 CPU. */
if (has_feature (FEATURE_AVX))
{
+ /* Assume Granite Rapids. */
+ if (has_feature (FEATURE_AMX_FP16))
+ cpu = "graniterapids";
/* Assume Sierra Forest. */
- if (has_feature (FEATURE_AVXVNNIINT8))
+ else if (has_feature (FEATURE_AVXVNNIINT8))
cpu = "sierraforest";
/* Assume Tiger Lake */
else if (has_feature (FEATURE_AVX512VP2INTERSECT))
def_or_undef (parse_in, "__sapphirerapids");
def_or_undef (parse_in, "__sapphirerapids__");
break;
+ case PROCESSOR_GRANITERAPIDS:
+ def_or_undef (parse_in, "__graniterapids");
+ def_or_undef (parse_in, "__graniterapids__");
+ break;
case PROCESSOR_ALDERLAKE:
def_or_undef (parse_in, "__alderlake");
def_or_undef (parse_in, "__alderlake__");
case PROCESSOR_ROCKETLAKE:
def_or_undef (parse_in, "__tune_rocketlake__");
break;
+ case PROCESSOR_GRANITERAPIDS:
+ def_or_undef (parse_in, "__tune_graniterapids__");
+ break;
case PROCESSOR_INTEL:
case PROCESSOR_GENERIC:
break;
#define m_SAPPHIRERAPIDS (HOST_WIDE_INT_1U<<PROCESSOR_SAPPHIRERAPIDS)
#define m_ALDERLAKE (HOST_WIDE_INT_1U<<PROCESSOR_ALDERLAKE)
#define m_ROCKETLAKE (HOST_WIDE_INT_1U<<PROCESSOR_ROCKETLAKE)
+#define m_GRANITERAPIDS (HOST_WIDE_INT_1U<<PROCESSOR_GRANITERAPIDS)
#define m_CORE_AVX512 (m_SKYLAKE_AVX512 | m_CANNONLAKE \
| m_ICELAKE_CLIENT | m_ICELAKE_SERVER | m_CASCADELAKE \
| m_TIGERLAKE | m_COOPERLAKE | m_SAPPHIRERAPIDS \
- | m_ROCKETLAKE)
+ | m_ROCKETLAKE | m_GRANITERAPIDS)
#define m_CORE_AVX2 (m_HASWELL | m_SKYLAKE | m_CORE_AVX512)
#define m_CORE_ALL (m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_CORE_AVX2)
#define m_GOLDMONT (HOST_WIDE_INT_1U<<PROCESSOR_GOLDMONT)
&icelake_cost,
&alderlake_cost,
&icelake_cost,
+ &icelake_cost,
&intel_cost,
&lujiazui_cost,
&geode_cost,
PROCESSOR_SAPPHIRERAPIDS,
PROCESSOR_ALDERLAKE,
PROCESSOR_ROCKETLAKE,
+ PROCESSOR_GRANITERAPIDS,
PROCESSOR_INTEL,
PROCESSOR_LUJIAZUI,
PROCESSOR_GEODE,
| PTA_HRESET | PTA_KL | PTA_WIDEKL | PTA_AVXVNNI;
constexpr wide_int_bitmask PTA_SIERRAFOREST = PTA_ALDERLAKE | PTA_AVXIFMA
| PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD;
+constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16
+ | PTA_PREFETCHI;
constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW
| PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ;
constexpr wide_int_bitmask PTA_ZNVER1 = PTA_64BIT | PTA_MMX | PTA_SSE | PTA_SSE2
@item rocketlake
Intel Core i7 Rocketlake CPU.
+@item graniterapids
+Intel Core i7 graniterapids CPU.
+
@item bonnell
Intel Atom Bonnell CPU.
PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2,
VPCLMULQDQ, AVX512BITALG, RDPID and AVX512VPOPCNTDQ instruction set support.
+@item graniterapids
+Intel graniterapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
+SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,
+RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,
+AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ,
+AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2,
+VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB,
+MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,
+SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI, AVX512FP16,
+AVX512BF16, AMX-FP16 and PREFETCHI instruction set support.
+
@item k6
AMD K6 CPU with MMX instruction set support.
return 25;
}
+int __attribute__ ((target("arch=graniterapids"))) foo () {
+ return 26;
+}
+
int main ()
{
int val = foo ();
assert (val == 24);
else if (__builtin_cpu_is ("sierraforest"))
assert (val == 25);
+ else if (__builtin_cpu_is ("graniterapids"))
+ assert (val == 26);
else
assert (val == 0);
extern void test_arch_sapphirerapids (void) __attribute__((__target__("arch=sapphirerapids")));
extern void test_arch_alderlake (void) __attribute__((__target__("arch=alderlake")));
extern void test_arch_rocketlake (void) __attribute__((__target__("arch=rocketlake")));
+extern void test_arch_graniterapids (void) __attribute__((__target__("arch=graniterapids")));
extern void test_arch_lujiazui (void) __attribute__((__target__("arch=lujiazui")));
extern void test_arch_k8 (void) __attribute__((__target__("arch=k8")));
extern void test_arch_k8_sse3 (void) __attribute__((__target__("arch=k8-sse3")));