x86/bugs: Rename SSBD_NO to SSB_NO
authorKonrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Thu, 17 May 2018 03:18:09 +0000 (23:18 -0400)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 22 May 2018 14:58:04 +0000 (16:58 +0200)
commit 240da953fcc6a9008c92fae5b1f727ee5ed167ab upstream

The "336996 Speculative Execution Side Channel Mitigations" from
May defines this as SSB_NO, hence lets sync-up.

Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: David Woodhouse <dwmw@amazon.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/x86/include/asm/msr-index.h
arch/x86/kernel/cpu/common.c

index 9fd9dcfe179e72bca5f96207ff86dea95c8334f7..1ec13e25317419f8fd03811a05e3c84803e5cb0c 100644 (file)
@@ -63,7 +63,7 @@
 #define MSR_IA32_ARCH_CAPABILITIES     0x0000010a
 #define ARCH_CAP_RDCL_NO               (1 << 0)   /* Not susceptible to Meltdown */
 #define ARCH_CAP_IBRS_ALL              (1 << 1)   /* Enhanced IBRS support */
-#define ARCH_CAP_SSBD_NO               (1 << 4)   /*
+#define ARCH_CAP_SSB_NO                        (1 << 4)   /*
                                                    * Not susceptible to Speculative Store Bypass
                                                    * attack, so no Speculative Store Bypass
                                                    * control required.
index 40fc748f60f68535db907983f232c9ca66524b24..b0fd028b2eeedfebe4ebb52de5aeafd21b4b7c8a 100644 (file)
@@ -926,7 +926,7 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
                rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap);
 
        if (!x86_match_cpu(cpu_no_spec_store_bypass) &&
-          !(ia32_cap & ARCH_CAP_SSBD_NO))
+          !(ia32_cap & ARCH_CAP_SSB_NO))
                setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
 
        if (x86_match_cpu(cpu_no_speculation))