ARM: tegra: update DT files to add reset properties
authorStephen Warren <swarren@nvidia.com>
Wed, 6 Nov 2013 21:01:16 +0000 (14:01 -0700)
committerStephen Warren <swarren@nvidia.com>
Wed, 11 Dec 2013 23:42:32 +0000 (16:42 -0700)
An earlier patch updated the Tegra DT bindings to require resets and
reset-names properties to be filled in. This patch updates the DT files
to include those properties.

Note that any legacy clocks and clock-names entries that are replaced by
reset properties are not yet removed; the drivers must be updated to use
the new resets and reset-names properties first.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
arch/arm/boot/dts/tegra114.dtsi
arch/arm/boot/dts/tegra20-paz00.dts
arch/arm/boot/dts/tegra20.dtsi
arch/arm/boot/dts/tegra30.dtsi

index 8d42787..c40dbdc 100644 (file)
@@ -43,6 +43,7 @@
                compatible = "nvidia,tegra114-car";
                reg = <0x60006000 0x1000>;
                #clock-cells = <1>;
+               #reset-cells = <1>;
        };
 
        apbdma: dma {
@@ -81,6 +82,8 @@
                             <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA114_CLK_APBDMA>;
+               resets = <&tegra_car 34>;
+               reset-names = "dma";
        };
 
        ahb: ahb {
                reg-shift = <2>;
                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 8>;
-               status = "disabled";
                clocks = <&tegra_car TEGRA114_CLK_UARTA>;
+               resets = <&tegra_car 6>;
+               reset-names = "serial";
+               status = "disabled";
        };
 
        uartb: serial@70006040 {
                reg-shift = <2>;
                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 9>;
-               status = "disabled";
                clocks = <&tegra_car TEGRA114_CLK_UARTB>;
+               resets = <&tegra_car 7>;
+               reset-names = "serial";
+               status = "disabled";
        };
 
        uartc: serial@70006200 {
                reg-shift = <2>;
                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 10>;
-               status = "disabled";
                clocks = <&tegra_car TEGRA114_CLK_UARTC>;
+               resets = <&tegra_car 55>;
+               reset-names = "serial";
+               status = "disabled";
        };
 
        uartd: serial@70006300 {
                reg-shift = <2>;
                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 19>;
-               status = "disabled";
                clocks = <&tegra_car TEGRA114_CLK_UARTD>;
+               resets = <&tegra_car 65>;
+               reset-names = "serial";
+               status = "disabled";
        };
 
        pwm: pwm {
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
                clocks = <&tegra_car TEGRA114_CLK_PWM>;
+               resets = <&tegra_car 17>;
+               reset-names = "pwm";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA114_CLK_I2C1>;
                clock-names = "div-clk";
+               resets = <&tegra_car 12>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA114_CLK_I2C2>;
                clock-names = "div-clk";
+               resets = <&tegra_car 54>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA114_CLK_I2C3>;
                clock-names = "div-clk";
+               resets = <&tegra_car 67>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA114_CLK_I2C4>;
                clock-names = "div-clk";
+               resets = <&tegra_car 103>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA114_CLK_I2C5>;
                clock-names = "div-clk";
+               resets = <&tegra_car 47>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA114_CLK_SBC1>;
                clock-names = "spi";
+               resets = <&tegra_car 41>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA114_CLK_SBC2>;
                clock-names = "spi";
+               resets = <&tegra_car 44>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA114_CLK_SBC3>;
                clock-names = "spi";
+               resets = <&tegra_car 46>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA114_CLK_SBC4>;
                clock-names = "spi";
+               resets = <&tegra_car 68>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA114_CLK_SBC5>;
                clock-names = "spi";
+               resets = <&tegra_car 104>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA114_CLK_SBC6>;
                clock-names = "spi";
+               resets = <&tegra_car 105>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                reg = <0x7000e200 0x100>;
                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA114_CLK_KBC>;
+               resets = <&tegra_car 36>;
+               reset-names = "kbc";
                status = "disabled";
        };
 
                clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
                              "i2s3", "i2s4", "dam0", "dam1", "dam2",
                              "spdif_in", "amx", "adx";
+               resets = <&tegra_car 106>, /* d_audio */
+                        <&tegra_car 107>, /* apbif */
+                        <&tegra_car 30>,  /* i2s0 */
+                        <&tegra_car 11>,  /* i2s1 */
+                        <&tegra_car 18>,  /* i2s2 */
+                        <&tegra_car 101>, /* i2s3 */
+                        <&tegra_car 102>, /* i2s4 */
+                        <&tegra_car 108>, /* dam0 */
+                        <&tegra_car 109>, /* dam1 */
+                        <&tegra_car 110>, /* dam2 */
+                        <&tegra_car 10>,  /* spdif */
+                        <&tegra_car 153>, /* amx */
+                        <&tegra_car 154>; /* adx */
+               reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+                             "i2s3", "i2s4", "dam0", "dam1", "dam2",
+                             "spdif", "amx", "adx";
                ranges;
                #address-cells = <1>;
                #size-cells = <1>;
                        reg = <0x70080300 0x100>;
                        nvidia,ahub-cif-ids = <4 4>;
                        clocks = <&tegra_car TEGRA114_CLK_I2S0>;
+                       resets = <&tegra_car 30>;
+                       reset-names = "i2s";
                        status = "disabled";
                };
 
                        reg = <0x70080400 0x100>;
                        nvidia,ahub-cif-ids = <5 5>;
                        clocks = <&tegra_car TEGRA114_CLK_I2S1>;
+                       resets = <&tegra_car 11>;
+                       reset-names = "i2s";
                        status = "disabled";
                };
 
                        reg = <0x70080500 0x100>;
                        nvidia,ahub-cif-ids = <6 6>;
                        clocks = <&tegra_car TEGRA114_CLK_I2S2>;
+                       resets = <&tegra_car 18>;
+                       reset-names = "i2s";
                        status = "disabled";
                };
 
                        reg = <0x70080600 0x100>;
                        nvidia,ahub-cif-ids = <7 7>;
                        clocks = <&tegra_car TEGRA114_CLK_I2S3>;
+                       resets = <&tegra_car 101>;
+                       reset-names = "i2s";
                        status = "disabled";
                };
 
                        reg = <0x70080700 0x100>;
                        nvidia,ahub-cif-ids = <8 8>;
                        clocks = <&tegra_car TEGRA114_CLK_I2S4>;
+                       resets = <&tegra_car 102>;
+                       reset-names = "i2s";
                        status = "disabled";
                };
        };
                reg = <0x78000000 0x200>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA114_CLK_SDMMC1>;
+               resets = <&tegra_car 14>;
+               reset-names = "sdhci";
                status = "disable";
        };
 
                reg = <0x78000200 0x200>;
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA114_CLK_SDMMC2>;
+               resets = <&tegra_car 9>;
+               reset-names = "sdhci";
                status = "disable";
        };
 
                reg = <0x78000400 0x200>;
                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA114_CLK_SDMMC3>;
+               resets = <&tegra_car 69>;
+               reset-names = "sdhci";
                status = "disable";
        };
 
                reg = <0x78000600 0x200>;
                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA114_CLK_SDMMC4>;
+               resets = <&tegra_car 15>;
+               reset-names = "sdhci";
                status = "disable";
        };
 
                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                phy_type = "utmi";
                clocks = <&tegra_car TEGRA114_CLK_USBD>;
+               resets = <&tegra_car 22>;
+               reset-names = "usb";
                nvidia,phy = <&phy1>;
                status = "disabled";
        };
                interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                phy_type = "utmi";
                clocks = <&tegra_car TEGRA114_CLK_USB3>;
+               resets = <&tegra_car 59>;
+               reset-names = "usb";
                nvidia,phy = <&phy3>;
                status = "disabled";
        };
index 8d71fc9..e57fb3a 100644 (file)
                clocks = <&tegra_car TEGRA20_CLK_I2C3>,
                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 67>;
+               reset-names = "i2c";
        };
 
        i2c@7000d000 {
index 4eaeab3..f21b041 100644 (file)
@@ -22,6 +22,8 @@
                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
                clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
+               resets = <&tegra_car 28>;
+               reset-names = "host1x";
 
                #address-cells = <1>;
                #size-cells = <1>;
@@ -33,6 +35,8 @@
                        reg = <0x54040000 0x00040000>;
                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA20_CLK_MPE>;
+                       resets = <&tegra_car 60>;
+                       reset-names = "mpe";
                };
 
                vi {
@@ -40,6 +44,8 @@
                        reg = <0x54080000 0x00040000>;
                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA20_CLK_VI>;
+                       resets = <&tegra_car 20>;
+                       reset-names = "vi";
                };
 
                epp {
@@ -47,6 +53,8 @@
                        reg = <0x540c0000 0x00040000>;
                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA20_CLK_EPP>;
+                       resets = <&tegra_car 19>;
+                       reset-names = "epp";
                };
 
                isp {
@@ -54,6 +62,8 @@
                        reg = <0x54100000 0x00040000>;
                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA20_CLK_ISP>;
+                       resets = <&tegra_car 23>;
+                       reset-names = "isp";
                };
 
                gr2d {
                        reg = <0x54140000 0x00040000>;
                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA20_CLK_GR2D>;
+                       resets = <&tegra_car 21>;
+                       reset-names = "2d";
                };
 
                gr3d {
                        compatible = "nvidia,tegra20-gr3d";
                        reg = <0x54180000 0x00040000>;
                        clocks = <&tegra_car TEGRA20_CLK_GR3D>;
+                       resets = <&tegra_car 24>;
+                       reset-names = "3d";
                };
 
                dc@54200000 {
@@ -76,6 +90,8 @@
                        clocks = <&tegra_car TEGRA20_CLK_DISP1>,
                                 <&tegra_car TEGRA20_CLK_PLL_P>;
                        clock-names = "dc", "parent";
+                       resets = <&tegra_car 27>;
+                       reset-names = "dc";
 
                        rgb {
                                status = "disabled";
                        clocks = <&tegra_car TEGRA20_CLK_DISP2>,
                                 <&tegra_car TEGRA20_CLK_PLL_P>;
                        clock-names = "dc", "parent";
+                       resets = <&tegra_car 26>;
+                       reset-names = "dc";
 
                        rgb {
                                status = "disabled";
                        clocks = <&tegra_car TEGRA20_CLK_HDMI>,
                                 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
                        clock-names = "hdmi", "parent";
+                       resets = <&tegra_car 51>;
+                       reset-names = "hdmi";
                        status = "disabled";
                };
 
                        compatible = "nvidia,tegra20-dsi";
                        reg = <0x54300000 0x00040000>;
                        clocks = <&tegra_car TEGRA20_CLK_DSI>;
+                       resets = <&tegra_car 48>;
+                       reset-names = "dsi";
                        status = "disabled";
                };
        };
                compatible = "nvidia,tegra20-car";
                reg = <0x60006000 0x1000>;
                #clock-cells = <1>;
+               #reset-cells = <1>;
        };
 
        apbdma: dma {
                             <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
+               resets = <&tegra_car 34>;
+               reset-names = "dma";
        };
 
        ahb {
                interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 12>;
                clocks = <&tegra_car TEGRA20_CLK_AC97>;
+               resets = <&tegra_car 3>;
+               reset-names = "ac97";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 2>;
                clocks = <&tegra_car TEGRA20_CLK_I2S1>;
+               resets = <&tegra_car 11>;
+               reset-names = "i2s";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 1>;
                clocks = <&tegra_car TEGRA20_CLK_I2S2>;
+               resets = <&tegra_car 18>;
+               reset-names = "i2s";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 8>;
                clocks = <&tegra_car TEGRA20_CLK_UARTA>;
+               resets = <&tegra_car 6>;
+               reset-names = "serial";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 9>;
                clocks = <&tegra_car TEGRA20_CLK_UARTB>;
+               resets = <&tegra_car 7>;
+               reset-names = "serial";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 10>;
                clocks = <&tegra_car TEGRA20_CLK_UARTC>;
+               resets = <&tegra_car 55>;
+               reset-names = "serial";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 19>;
                clocks = <&tegra_car TEGRA20_CLK_UARTD>;
+               resets = <&tegra_car 65>;
+               reset-names = "serial";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 20>;
                clocks = <&tegra_car TEGRA20_CLK_UARTE>;
+               resets = <&tegra_car 66>;
+               reset-names = "serial";
                status = "disabled";
        };
 
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
                clocks = <&tegra_car TEGRA20_CLK_PWM>;
+               resets = <&tegra_car 17>;
+               reset-names = "pwm";
                status = "disabled";
        };
 
                clocks = <&tegra_car TEGRA20_CLK_I2C1>,
                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 12>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA20_CLK_SPI>;
+               resets = <&tegra_car 43>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                clocks = <&tegra_car TEGRA20_CLK_I2C2>,
                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 54>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                clocks = <&tegra_car TEGRA20_CLK_I2C3>,
                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 67>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                clocks = <&tegra_car TEGRA20_CLK_DVC>,
                         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 47>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA20_CLK_SBC1>;
+               resets = <&tegra_car 41>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA20_CLK_SBC2>;
+               resets = <&tegra_car 44>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA20_CLK_SBC3>;
+               resets = <&tegra_car 46>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA20_CLK_SBC4>;
+               resets = <&tegra_car 68>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                reg = <0x7000e200 0x100>;
                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA20_CLK_KBC>;
+               resets = <&tegra_car 36>;
+               reset-names = "kbc";
                status = "disabled";
        };
 
                         <&tegra_car TEGRA20_CLK_PCIE_XCLK>,
                         <&tegra_car TEGRA20_CLK_PLL_E>;
                clock-names = "pex", "afi", "pcie_xclk", "pll_e";
+               resets = <&tegra_car 70>,
+                        <&tegra_car 72>,
+                        <&tegra_car 74>;
+               reset-names = "pex", "afi", "pcie_x";
                status = "disabled";
 
                pci@1,0 {
                phy_type = "utmi";
                nvidia,has-legacy-mode;
                clocks = <&tegra_car TEGRA20_CLK_USBD>;
+               resets = <&tegra_car 22>;
+               reset-names = "usb";
                nvidia,needs-double-reset;
                nvidia,phy = <&phy1>;
                status = "disabled";
                interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
                phy_type = "ulpi";
                clocks = <&tegra_car TEGRA20_CLK_USB2>;
+               resets = <&tegra_car 58>;
+               reset-names = "usb";
                nvidia,phy = <&phy2>;
                status = "disabled";
        };
                interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                phy_type = "utmi";
                clocks = <&tegra_car TEGRA20_CLK_USB3>;
+               resets = <&tegra_car 59>;
+               reset-names = "usb";
                nvidia,phy = <&phy3>;
                status = "disabled";
        };
                reg = <0xc8000000 0x200>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
+               resets = <&tegra_car 14>;
+               reset-names = "sdhci";
                status = "disabled";
        };
 
                reg = <0xc8000200 0x200>;
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
+               resets = <&tegra_car 9>;
+               reset-names = "sdhci";
                status = "disabled";
        };
 
                reg = <0xc8000400 0x200>;
                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
+               resets = <&tegra_car 69>;
+               reset-names = "sdhci";
                status = "disabled";
        };
 
                reg = <0xc8000600 0x200>;
                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
+               resets = <&tegra_car 15>;
+               reset-names = "sdhci";
                status = "disabled";
        };
 
index 6e0e5a3..1e1a017 100644 (file)
                         <&tegra_car TEGRA30_CLK_PLL_E>,
                         <&tegra_car TEGRA30_CLK_CML0>;
                clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml";
+               resets = <&tegra_car 70>,
+                        <&tegra_car 72>,
+                        <&tegra_car 74>;
+               reset-names = "pex", "afi", "pcie_x";
                status = "disabled";
 
                pci@1,0 {
@@ -92,6 +96,8 @@
                interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
                             <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
                clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
+               resets = <&tegra_car 28>;
+               reset-names = "host1x";
 
                #address-cells = <1>;
                #size-cells = <1>;
                        reg = <0x54040000 0x00040000>;
                        interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA30_CLK_MPE>;
+                       resets = <&tegra_car 60>;
+                       reset-names = "mpe";
                };
 
                vi {
                        reg = <0x54080000 0x00040000>;
                        interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA30_CLK_VI>;
+                       resets = <&tegra_car 20>;
+                       reset-names = "vi";
                };
 
                epp {
                        reg = <0x540c0000 0x00040000>;
                        interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA30_CLK_EPP>;
+                       resets = <&tegra_car 19>;
+                       reset-names = "epp";
                };
 
                isp {
                        reg = <0x54100000 0x00040000>;
                        interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&tegra_car TEGRA30_CLK_ISP>;
+                       resets = <&tegra_car 23>;
+                       reset-names = "isp";
                };
 
                gr2d {
                        compatible = "nvidia,tegra30-gr2d";
                        reg = <0x54140000 0x00040000>;
                        interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+                       resets = <&tegra_car 21>;
+                       reset-names = "2d";
                        clocks = <&tegra_car TEGRA30_CLK_GR2D>;
                };
 
                        clocks = <&tegra_car TEGRA30_CLK_GR3D
                                  &tegra_car TEGRA30_CLK_GR3D2>;
                        clock-names = "3d", "3d2";
+                       resets = <&tegra_car 24>,
+                                <&tegra_car 98>;
+                       reset-names = "3d", "3d2";
                };
 
                dc@54200000 {
                        clocks = <&tegra_car TEGRA30_CLK_DISP1>,
                                 <&tegra_car TEGRA30_CLK_PLL_P>;
                        clock-names = "dc", "parent";
+                       resets = <&tegra_car 27>;
+                       reset-names = "dc";
 
                        rgb {
                                status = "disabled";
                        clocks = <&tegra_car TEGRA30_CLK_DISP2>,
                                 <&tegra_car TEGRA30_CLK_PLL_P>;
                        clock-names = "dc", "parent";
+                       resets = <&tegra_car 26>;
+                       reset-names = "dc";
 
                        rgb {
                                status = "disabled";
                        clocks = <&tegra_car TEGRA30_CLK_HDMI>,
                                 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
                        clock-names = "hdmi", "parent";
+                       resets = <&tegra_car 51>;
+                       reset-names = "hdmi";
                        status = "disabled";
                };
 
                        compatible = "nvidia,tegra30-dsi";
                        reg = <0x54300000 0x00040000>;
                        clocks = <&tegra_car TEGRA30_CLK_DSIA>;
+                       resets = <&tegra_car 48>;
+                       reset-names = "dsi";
                        status = "disabled";
                };
        };
                compatible = "nvidia,tegra30-car";
                reg = <0x60006000 0x1000>;
                #clock-cells = <1>;
+               #reset-cells = <1>;
        };
 
        apbdma: dma {
                             <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
                             <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
+               resets = <&tegra_car 34>;
+               reset-names = "dma";
        };
 
        ahb: ahb {
                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 8>;
                clocks = <&tegra_car TEGRA30_CLK_UARTA>;
+               resets = <&tegra_car 6>;
+               reset-names = "serial";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 9>;
                clocks = <&tegra_car TEGRA30_CLK_UARTB>;
+               resets = <&tegra_car 7>;
+               reset-names = "serial";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 10>;
                clocks = <&tegra_car TEGRA30_CLK_UARTC>;
+               resets = <&tegra_car 55>;
+               reset-names = "serial";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 19>;
                clocks = <&tegra_car TEGRA30_CLK_UARTD>;
+               resets = <&tegra_car 65>;
+               reset-names = "serial";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
                nvidia,dma-request-selector = <&apbdma 20>;
                clocks = <&tegra_car TEGRA30_CLK_UARTE>;
+               resets = <&tegra_car 66>;
+               reset-names = "serial";
                status = "disabled";
        };
 
                reg = <0x7000a000 0x100>;
                #pwm-cells = <2>;
                clocks = <&tegra_car TEGRA30_CLK_PWM>;
+               resets = <&tegra_car 17>;
+               reset-names = "pwm";
                status = "disabled";
        };
 
                clocks = <&tegra_car TEGRA30_CLK_I2C1>,
                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 12>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                clocks = <&tegra_car TEGRA30_CLK_I2C2>,
                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 54>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                clocks = <&tegra_car TEGRA30_CLK_I2C3>,
                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 67>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA30_CLK_I2C4>,
                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
+               resets = <&tegra_car 103>;
+               reset-names = "i2c";
                clock-names = "div-clk", "fast-clk";
                status = "disabled";
        };
                clocks = <&tegra_car TEGRA30_CLK_I2C5>,
                         <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
                clock-names = "div-clk", "fast-clk";
+               resets = <&tegra_car 47>;
+               reset-names = "i2c";
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA30_CLK_SBC1>;
+               resets = <&tegra_car 41>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA30_CLK_SBC2>;
+               resets = <&tegra_car 44>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA30_CLK_SBC3>;
+               resets = <&tegra_car 46>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA30_CLK_SBC4>;
+               resets = <&tegra_car 68>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA30_CLK_SBC5>;
+               resets = <&tegra_car 104>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                #address-cells = <1>;
                #size-cells = <0>;
                clocks = <&tegra_car TEGRA30_CLK_SBC6>;
+               resets = <&tegra_car 106>;
+               reset-names = "spi";
                status = "disabled";
        };
 
                reg = <0x7000e200 0x100>;
                interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA30_CLK_KBC>;
+               resets = <&tegra_car 36>;
+               reset-names = "kbc";
                status = "disabled";
        };
 
                clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
                              "i2s3", "i2s4", "dam0", "dam1", "dam2",
                              "spdif_in";
+               resets = <&tegra_car 106>, /* d_audio */
+                        <&tegra_car 107>, /* apbif */
+                        <&tegra_car 30>,  /* i2s0 */
+                        <&tegra_car 11>,  /* i2s1 */
+                        <&tegra_car 18>,  /* i2s2 */
+                        <&tegra_car 101>, /* i2s3 */
+                        <&tegra_car 102>, /* i2s4 */
+                        <&tegra_car 108>, /* dam0 */
+                        <&tegra_car 109>, /* dam1 */
+                        <&tegra_car 110>, /* dam2 */
+                        <&tegra_car 10>;  /* spdif */
+               reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
+                             "i2s3", "i2s4", "dam0", "dam1", "dam2",
+                             "spdif";
                ranges;
                #address-cells = <1>;
                #size-cells = <1>;
                        reg = <0x70080300 0x100>;
                        nvidia,ahub-cif-ids = <4 4>;
                        clocks = <&tegra_car TEGRA30_CLK_I2S0>;
+                       resets = <&tegra_car 30>;
+                       reset-names = "i2s";
                        status = "disabled";
                };
 
                        reg = <0x70080400 0x100>;
                        nvidia,ahub-cif-ids = <5 5>;
                        clocks = <&tegra_car TEGRA30_CLK_I2S1>;
+                       resets = <&tegra_car 11>;
+                       reset-names = "i2s";
                        status = "disabled";
                };
 
                        reg = <0x70080500 0x100>;
                        nvidia,ahub-cif-ids = <6 6>;
                        clocks = <&tegra_car TEGRA30_CLK_I2S2>;
+                       resets = <&tegra_car 18>;
+                       reset-names = "i2s";
                        status = "disabled";
                };
 
                        reg = <0x70080600 0x100>;
                        nvidia,ahub-cif-ids = <7 7>;
                        clocks = <&tegra_car TEGRA30_CLK_I2S3>;
+                       resets = <&tegra_car 101>;
+                       reset-names = "i2s";
                        status = "disabled";
                };
 
                        reg = <0x70080700 0x100>;
                        nvidia,ahub-cif-ids = <8 8>;
                        clocks = <&tegra_car TEGRA30_CLK_I2S4>;
+                       resets = <&tegra_car 102>;
+                       reset-names = "i2s";
                        status = "disabled";
                };
        };
                reg = <0x78000000 0x200>;
                interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
+               resets = <&tegra_car 14>;
+               reset-names = "sdhci";
                status = "disabled";
        };
 
                reg = <0x78000200 0x200>;
                interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
+               resets = <&tegra_car 9>;
+               reset-names = "sdhci";
                status = "disabled";
        };
 
                reg = <0x78000400 0x200>;
                interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
+               resets = <&tegra_car 69>;
+               reset-names = "sdhci";
                status = "disabled";
        };
 
                reg = <0x78000600 0x200>;
                interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
+               resets = <&tegra_car 15>;
+               reset-names = "sdhci";
                status = "disabled";
        };
 
                interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
                phy_type = "utmi";
                clocks = <&tegra_car TEGRA30_CLK_USBD>;
+               resets = <&tegra_car 22>;
+               reset-names = "usb";
                nvidia,needs-double-reset;
                nvidia,phy = <&phy1>;
                status = "disabled";
                interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
                phy_type = "ulpi";
                clocks = <&tegra_car TEGRA30_CLK_USB2>;
+               resets = <&tegra_car 58>;
+               reset-names = "usb";
                nvidia,phy = <&phy2>;
                status = "disabled";
        };
                interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                phy_type = "utmi";
                clocks = <&tegra_car TEGRA30_CLK_USB3>;
+               resets = <&tegra_car 59>;
+               reset-names = "usb";
                nvidia,phy = <&phy3>;
                status = "disabled";
        };