clk: mxl: Fix a clk entry by adding relevant flags

[ Upstream commit 106ef3bda21006fe37b62c85931230a6355d78d3 ]

One of the clock entry "dcl" clk has some HW limitations. One is that
its rate can only by changed by changing its parent clk's rate & two is
that HW does not support enable/disable for this clk.

Handle above two limitations by adding relevant flags. Add standard flag
CLK_SET_RATE_PARENT to handle rate change and add driver internal flag
DIV_CLK_NO_MASK to handle enable/disable.

Fixes: d058fd9e8984 ("clk: intel: Add CGU clock driver for a new SoC")
Reviewed-by: Yi xin Zhu <yzhu@maxlinear.com>
Signed-off-by: Rahul Tanwar <rtanwar@maxlinear.com>
Link: https://lore.kernel.org/r/a4770e7225f8a0c03c8ab2ba80434a4e8e9afb17.1665642720.git.rtanwar@maxlinear.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/drivers/clk/x86/clk-cgu.c b/drivers/clk/x86/clk-cgu.c
index 4278a687076c939f3bd084fe8be1d931041c4624..89b53f280aee03b7838e4656eae3571f00eaa263 100644 (file)
--- a/drivers/clk/x86/clk-cgu.c
+++ b/drivers/clk/x86/clk-cgu.c
@@ -164,8 +164,9 @@ static int lgm_clk_divider_enable_disable(struct clk_hw *hw, int enable)
 {
        struct lgm_clk_divider *div = to_lgm_clk_divider(hw);
 
-       lgm_set_clk_val(div->membase, div->reg, div->shift_gate,
-                       div->width_gate, enable);
+       if (div->flags != DIV_CLK_NO_MASK)
+               lgm_set_clk_val(div->membase, div->reg, div->shift_gate,
+                               div->width_gate, enable);
        return 0;
 }
 

diff --git a/drivers/clk/x86/clk-cgu.h b/drivers/clk/x86/clk-cgu.h
index 73ce84345f81e34337e6751865b78fc17efb7a60..bcaf8aec94e5d3d166d7fd6149c4e97ca039847c 100644 (file)
--- a/drivers/clk/x86/clk-cgu.h
+++ b/drivers/clk/x86/clk-cgu.h
@@ -198,6 +198,7 @@ struct lgm_clk_branch {
 #define CLOCK_FLAG_VAL_INIT    BIT(16)
 #define MUX_CLK_SW             BIT(17)
 #define GATE_CLK_HW            BIT(18)
+#define DIV_CLK_NO_MASK                BIT(19)
 
 #define LGM_MUX(_id, _name, _pdata, _f, _reg,          \
                _shift, _width, _cf, _v)                \

diff --git a/drivers/clk/x86/clk-lgm.c b/drivers/clk/x86/clk-lgm.c
index e312af42e97ae1024d18b86bb6ecdf18814c2129..4de77b2c750d37c3ae7c31fd31fe407375e38559 100644 (file)
--- a/drivers/clk/x86/clk-lgm.c
+++ b/drivers/clk/x86/clk-lgm.c
@@ -255,8 +255,8 @@ static const struct lgm_clk_branch lgm_branch_clks[] = {
        LGM_FIXED(LGM_CLK_SLIC, "slic", NULL, 0, CGU_IF_CLK1,
                  8, 2, CLOCK_FLAG_VAL_INIT, 8192000, 2),
        LGM_FIXED(LGM_CLK_DOCSIS, "v_docsis", NULL, 0, 0, 0, 0, 0, 16000000, 0),
-       LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", 0, CGU_PCMCR,
-               25, 3, 0, 0, 0, 0, dcl_div),
+       LGM_DIV(LGM_CLK_DCL, "dcl", "v_ifclk", CLK_SET_RATE_PARENT, CGU_PCMCR,
+               25, 3, 0, 0, DIV_CLK_NO_MASK, 0, dcl_div),
        LGM_MUX(LGM_CLK_PCM, "pcm", pcm_p, 0, CGU_C55_PCMCR,
                0, 1, CLK_MUX_ROUND_CLOSEST, 0),
        LGM_FIXED_FACTOR(LGM_CLK_DDR_PHY, "ddr_phy", "ddr",