[AVX512] Stop treating VR512 specially in getLoadStoreRegOpcode and use the regular...

llvm-svn: 277302

diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
index fc346cb..b6f6a98 100644 (file)
--- a/llvm/lib/Target/X86/X86InstrInfo.cpp
+++ b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -4845,8 +4845,6 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
-    if (X86::VR512RegClass.hasSubClassEq(RC))
-      return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
   }
 
   bool HasAVX = STI.hasAVX();
@@ -4924,7 +4922,7 @@ static unsigned getLoadStoreRegOpcode(unsigned Reg,
       return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr;
   case 64:
     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
-    assert(STI.hasVLX() && "Using 512-bit register requires AVX512");
+    assert(STI.hasAVX512() && "Using 512-bit register requires AVX512");
     if (isStackAligned)
       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
     else

diff --git a/llvm/test/CodeGen/X86/avx512-intel-ocl.ll b/llvm/test/CodeGen/X86/avx512-intel-ocl.ll
index 69e06f5..44658be 100644 (file)
--- a/llvm/test/CodeGen/X86/avx512-intel-ocl.ll
+++ b/llvm/test/CodeGen/X86/avx512-intel-ocl.ll
@@ -62,11 +62,11 @@ define <16 x float> @testf16_regs(<16 x float> %a, <16 x float> %b) nounwind {
 
 ; test calling conventions - prolog and epilog
 ; WIN64-LABEL: test_prolog_epilog
-; WIN64: vmovups %zmm21, {{.*(%rbp).*}}     # 64-byte Spill
-; WIN64: vmovups %zmm6, {{.*(%rbp).*}}     # 64-byte Spill
+; WIN64: vmovaps %zmm21, {{.*(%rbp).*}}     # 64-byte Spill
+; WIN64: vmovaps %zmm6, {{.*(%rbp).*}}     # 64-byte Spill
 ; WIN64: call
-; WIN64: vmovups {{.*(%rbp).*}}, %zmm6      # 64-byte Reload
-; WIN64: vmovups {{.*(%rbp).*}}, %zmm21     # 64-byte Reload
+; WIN64: vmovaps {{.*(%rbp).*}}, %zmm6      # 64-byte Reload
+; WIN64: vmovaps {{.*(%rbp).*}}, %zmm21     # 64-byte Reload
 
 ; X64-LABEL: test_prolog_epilog
 ; X64:  kmovq   %k7, {{.*}}(%rsp)         ## 8-byte Spill