[AArch64] Enable CLI for Armv8.6-A f64mm

This patch is necessary for sve-ld1ro intrinsic I posted in
https://gcc.gnu.org/ml/gcc-patches/2020-01/msg00466.html .

I had mistakenly thought this option was already enabled upstream.

This provides the option +f64mm, that turns on the 64 bit floating point
matrix multiply extension.  This extension is only available for
AArch64.  Turning on this extension also turns on the SVE extension.

This extension is optional and only available at Armv8.2-A and onward.

We also add the ACLE defined macro for this extension.

gcc/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

	* config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
	Introduce this ACLE specified predefined macro.
	* config/aarch64/aarch64-option-extensions.def (f64mm): New.
	(fp): Disabling this disables f64mm.
	(simd): Disabling this disables f64mm.
	(fp16): Disabling this disables f64mm.
	(sve): Disabling this disables f64mm.
	* config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
	(AARCH64_ISA_F64MM): New.
	(TARGET_F64MM): New.
	* doc/invoke.texi (f64mm): Document new option.

gcc/testsuite/ChangeLog:

2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>

	* gcc.target/aarch64/pragma_cpp_predefs_2.c: Check for f64mm
	predef.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index debd4d7..39914e1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,17 @@
+2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * config/aarch64/aarch64-c.c (_ARM_FEATURE_MATMUL_FLOAT64):
+       Introduce this ACLE specified predefined macro.
+       * config/aarch64/aarch64-option-extensions.def (f64mm): New.
+       (fp): Disabling this disables f64mm.
+       (simd): Disabling this disables f64mm.
+       (fp16): Disabling this disables f64mm.
+       (sve): Disabling this disables f64mm.
+       * config/aarch64/aarch64.h (AARCH64_FL_F64MM): New.
+       (AARCH64_ISA_F64MM): New.
+       (TARGET_F64MM): New.
+       * doc/invoke.texi (f64mm): Document new option.
+
 2020-01-17  Wilco Dijkstra  <wdijkstr@arm.com>
 
        * config/aarch64/aarch64.c (generic_tunings): Add branch fusion.

diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c
index b422530..0020105 100644 (file)
--- a/gcc/config/aarch64/aarch64-c.c
+++ b/gcc/config/aarch64/aarch64-c.c
@@ -171,6 +171,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
   aarch64_def_or_undef (TARGET_MEMTAG, "__ARM_FEATURE_MEMORY_TAGGING", pfile);
 
   aarch64_def_or_undef (TARGET_I8MM, "__ARM_FEATURE_MATMUL_INT8", pfile);
+  aarch64_def_or_undef (TARGET_F64MM, "__ARM_FEATURE_MATMUL_FP64", pfile);
   aarch64_def_or_undef (TARGET_BF16_SIMD,
                        "__ARM_FEATURE_BF16_VECTOR_ARITHMETIC", pfile);
   aarch64_def_or_undef (TARGET_BF16_FP,

diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def
index 5022a1b..548f3e2 100644 (file)
--- a/gcc/config/aarch64/aarch64-option-extensions.def
+++ b/gcc/config/aarch64/aarch64-option-extensions.def
@@ -53,26 +53,26 @@
 /* Enabling "fp" just enables "fp".
    Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2",
    "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
-   "sve2-bitperm", "i8mm" and "bf16".  */
+   "sve2-bitperm", "i8mm", "f64mm", and "bf16".  */
 AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | \
                      AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | \
                      AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | \
                      AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
                      AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
                      AARCH64_FL_SVE2_BITPERM | AARCH64_FL_I8MM | \
-                     AARCH64_FL_BF16, false, "fp")
+                     AARCH64_FL_F64MM | AARCH64_FL_BF16, false, "fp")
 
 /* Enabling "simd" also enables "fp".
    Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3",
    "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4",
-   "sve2-bitperm", and "i8mm".  */
+   "sve2-bitperm", "i8mm", and "f64mm".  */
 AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, \
                      AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | \
                      AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | \
                      AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
                      AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
                      AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM | \
-                     AARCH64_FL_I8MM, false, \
+                     AARCH64_FL_I8MM | AARCH64_FL_F64MM, false, \
                      "asimd")
 
 /* Enabling "crypto" also enables "fp", "simd", "aes" and "sha2".
@@ -92,12 +92,13 @@ AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, false, "crc32")
 AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, false, "atomics")
 
 /* Enabling "fp16" also enables "fp".
-   Disabling "fp16" disables "fp16", "fp16fml", "sve", "sve2", "sve2-aes",
-   "sve2-sha3", "sve2-sm4", and "bitperm".  */
+   Disabling "fp16" disables "fp16", "fp16fml", "sve", "sve2",
+   "sve2-aes", "sve2-sha3", "sve2-sm4", "sve2-bitperm", and "f64mm".  */
 AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, \
-                     AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_SVE2 | \
-                     AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
-                     AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, \
+                     AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_F64MM | \
+                     AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
+                     AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
+                     AARCH64_FL_SVE2_BITPERM, false, \
                      "fphp asimdhp")
 
 /* Enabling or disabling "rcpc" only changes "rcpc".  */
@@ -140,12 +141,13 @@ AARCH64_OPT_EXTENSION("fp16fml", AARCH64_FL_F16FML, \
                      AARCH64_FL_FP | AARCH64_FL_F16, 0, false, "asimdfhm")
 
 /* Enabling "sve" also enables "fp16", "fp" and "simd".
-   Disabling "sve" disables "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4"
-   and "sve2-bitperm".  */
+   Disabling "sve" disables "sve", "f64mm", "sve2", "sve2-aes", "sve2-sha3",
+   "sve2-sm4" and "sve2-bitperm".  */
 AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | \
-                     AARCH64_FL_F16, AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | \
-                     AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | \
-                     AARCH64_FL_SVE2_BITPERM, false, "sve")
+                     AARCH64_FL_F16, AARCH64_FL_F64MM | AARCH64_FL_SVE2 | \
+                     AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | \
+                     AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, \
+                     false, "sve")
 
 /* Enabling/Disabling "profile" does not enable/disable any other feature.  */
 AARCH64_OPT_EXTENSION("profile", AARCH64_FL_PROFILE, 0, 0, false, "")
@@ -205,6 +207,12 @@ AARCH64_OPT_EXTENSION("tme", AARCH64_FL_TME, 0, 0, false, "")
 AARCH64_OPT_EXTENSION("i8mm", AARCH64_FL_I8MM, \
                      AARCH64_FL_SIMD | AARCH64_FL_FP, 0, false, "i8mm")
 
+/* Enabling "f64mm" also enables "sve", "fp16", "fp", and "simd".
+   Disabling "f64mm" only disables "f64mm".  */
+AARCH64_OPT_EXTENSION("f64mm", AARCH64_FL_F64MM, \
+                     AARCH64_FL_SVE | AARCH64_FL_F16 | AARCH64_FL_FP | \
+                     AARCH64_FL_SIMD, 0, false, "f64mm")
+
 /* Enabling "bf16" also enables "simd" and "fp".
    Disabling "bf16" only disables "bf16".  */
 AARCH64_OPT_EXTENSION("bf16", AARCH64_FL_BF16, \

diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h
index f46b01c..eac2d62 100644 (file)
--- a/gcc/config/aarch64/aarch64.h
+++ b/gcc/config/aarch64/aarch64.h
@@ -211,6 +211,9 @@ extern unsigned aarch64_architecture_version;
 /* Brain half-precision floating-point (BFloat16) Extension.  */
 #define AARCH64_FL_BF16              (1ULL << 36)
 
+/* 8-bit Integer Matrix Multiply (F64MM) extensions.  */
+#define AARCH64_FL_F64MM      (1ULL << 37)
+
 /* Has FP and SIMD.  */
 #define AARCH64_FL_FPSIMD     (AARCH64_FL_FP | AARCH64_FL_SIMD)
 
@@ -267,6 +270,7 @@ extern unsigned aarch64_architecture_version;
 #define AARCH64_ISA_MEMTAG        (aarch64_isa_flags & AARCH64_FL_MEMTAG)
 #define AARCH64_ISA_V8_6          (aarch64_isa_flags & AARCH64_FL_V8_6)
 #define AARCH64_ISA_I8MM          (aarch64_isa_flags & AARCH64_FL_I8MM)
+#define AARCH64_ISA_F64MM         (aarch64_isa_flags & AARCH64_FL_F64MM)
 #define AARCH64_ISA_BF16          (aarch64_isa_flags & AARCH64_FL_BF16)
 
 /* Crypto is an optional extension to AdvSIMD.  */
@@ -342,6 +346,9 @@ extern unsigned aarch64_architecture_version;
 /* I8MM instructions are enabled through +i8mm.  */
 #define TARGET_I8MM (AARCH64_ISA_I8MM)
 
+/* F64MM instructions are enabled through +f64mm.  */
+#define TARGET_F64MM (AARCH64_ISA_F64MM)
+
 /* BF16 instructions are enabled through +bf16.  */
 #define TARGET_BF16_FP (AARCH64_ISA_BF16)
 #define TARGET_BF16_SIMD (AARCH64_ISA_BF16 && TARGET_SIMD)

diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 2bf12a6..355bf1b 100644 (file)
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -16970,6 +16970,10 @@ Enable 8-bit Integer Matrix Multiply instructions.  This also enables
 Advanced SIMD and floating-point instructions.  This option is enabled by
 default for @option{-march=armv8.6-a}.  Use of this option with architectures
 prior to Armv8.2-A is not supported.
+@item f64mm
+Enable 64-bit Floating point Matrix Multiply instructions.  This also enables
+SVE instructions.  Use of this option with architectures prior to Armv8.2-A is
+not supported.
 @item bf16
 Enable brain half-precision floating-point instructions.  This also enables
 Advanced SIMD and floating-point instructions.  This option is enabled by

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 53c7efc..de3fe13 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-01-17  Matthew Malcomson  <matthew.malcomson@arm.com>
+
+       * gcc.target/aarch64/pragma_cpp_predefs_2.c: Check for f64mm
+       predef.
+
 2020-01-17  Jakub Jelinek  <jakub@redhat.com>
 
        PR c++/93228

diff --git a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
index f61d635..27d475f 100644 (file)
--- a/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
+++ b/gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
@@ -22,11 +22,18 @@
 #error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"
 #endif
 
+#ifdef __ARM_FEATURE_MATMUL_FP64
+#error "__ARM_FEATURE_MATMUL_FP64 is defined but should not be!"
+#endif
+
 #pragma GCC push_options
 #pragma GCC target ("arch=armv8.6-a")
 #ifndef __ARM_FEATURE_MATMUL_INT8
 #error "__ARM_FEATURE_MATMUL_INT8 is not defined but should be!"
 #endif
+#ifdef __ARM_FEATURE_MATMUL_FP64
+#error "__ARM_FEATURE_MATMUL_FP64 is defined but should not be!"
+#endif
 #pragma GCC pop_options
 
 #pragma GCC push_options
@@ -37,6 +44,13 @@
 #pragma GCC pop_options
 
 #pragma GCC push_options
+#pragma GCC target ("arch=armv8.2-a+f64mm")
+#ifndef __ARM_FEATURE_MATMUL_FP64
+#error "__ARM_FEATURE_MATMUL_FP64 is not defined but should be!"
+#endif
+#pragma GCC pop_options
+
+#pragma GCC push_options
 #pragma GCC target ("arch=armv8.6-a+nosimd")
 #ifdef __ARM_FEATURE_MATMUL_INT8
 #error "__ARM_FEATURE_MATMUL_INT8 is defined but should not be!"